V.D. Kunz

Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation

Application of double gate or surround-gate vertical metal oxide semiconductor field effect transistors (MOSFETs) is hindered by the parasitic overlap capacitance associated with their layout, which is considerably larger than for a lateral MOSFET on the same technology node. A simple self-aligned process has been developed to reduce the parasitic overlap capacitance in vertical MOSFETs using nitride spacers on the sidewalls of the trench or pillar and a local oxidation. This will result in an oxide layer on all exposed planar surfaces, but no oxide layer on the protected vertical channel area of the pillar. The encroachment of the oxide on the side of the pillar is studied by transmission electron microscopy (TEM) which is used to calibrate the nitride viscosity in the process simulations. Surround gate vertical transistors incorporating the spacer oxidation have been fabricated, and these transistors show the integrity of the process and excellent subthreshold slope and drive current. The reduction in intrinsic capacitance is calculated to be a factor of three. Pillar capacitors with a more advanced process have been fabricated and the total measured capacitance is reduced by a factor of five compared with structures without the spacer oxidation. Device simulations confirm the measured reduction in capacitance.

Design of 50-nm vertical MOSFET incorporating a dielectric pocket

A new architecture for a vertical MOS transistor is proposed that incorporates a so-called dielectric pocket (DP) for suppression of short-channel effects and bulk punch-through. We outline the advantages that the DP brings and propose a basic fabrication process to realize the device. The design issues of a 50-nm channel device are addressed by numerical simulation. The gate delay of an associated CMOS inverter is assessed in the context of the International Technology Roadmap for Semiconductors and the vertical transistor is seen to offer considerable advantages down to the 100-nm node and beyond due to the dual channels and the ability to produce a 50-nm channel length with more relaxed lithography.

Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from -50 to 200/spl deg/C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain-body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical <110> pillar sidewalls and the horizontal <100> wafer surface.

Polycrystalline silicon-germanium emitters for gain control, with application to SiGe HBTs

This paper investigates germanium incorporation into polysilicon emitters for gain control in SiGe heterojunction bipolar transistors. A theory for the base current of a polySiGe emitter is developed, which combines the effects of the polySiGe grains, the grain boundaries and the interfacial layer at the polySiGe/Si interface into an expression for the effective surface recombination velocity of a polySiGe emitter. Silicon bipolar transistors are fabricated with 0, 10 and 19% Ge in the polySiGe emitter and the variation of base current with Ge content is characterized. The measured base current for a polySiGe emitter increases by a factor of 3.2 for 10% Ge and 4.0 for 19% Ge compared with a control transistor containing no germanium. These values are in good agreement with the theoretical predictions. The competing mechanisms of base current increase by Ge incorporation into the polysilicon and base current decrease due to an interfacial oxide layer are investigated.

A 50nm channel vertical MOSFET concept incorporating a retrograde channel and a dielectric pocket

A novel architecture for a vertical MOSFET is proposed and initial investigations conducted by numerical simulation.

CMOS-compatible vertical MOSFETs and logic gates with reduced parasitic capacitance

This paper reports electrical results on CMOS-compatible vertical transistors and logic gates with reduced overlap capacitance. It is shown that surround-gate MOSFETs, produced using the fillet local oxidation process (FILOX), have lower gate/drain overlap capacitance and consume less silicon area than comparable lateral MOSFETs. Novel logic gate structures, based on partially removing the polysilicon surround gate, are described and characterised.

Electrical characteristics of single, double & surround gate vertical MOSFETs with reduced overlap capacitance

The vertical MOSFET structure is one of the solutions for reducing the channel length of devices under 50 nm. Surround gate structures can be realized which offer improved short channel effects and more channel width per unit silicon area. In this paper, a low overlap capacitance, surround gate, vertical MOSFET technology is presented, which uses fillet local oxidation (FILOX) to reduce the overlap capacitance between the gate and the drain on the bottom of the pillar. Electrical characteristics of surround gate n-MOSFETs are presented and compared with results from single gate and double gate devices on the same wafer. The devices show good symmetry between the source on top and source on bottom configuration. The short channel effects of the surround gate MOSFETs are investigated.

Application of Polycrystalline SiGe for Gain Control in SiGe Heterojunction Bipolar Transistors

This paper reports a method of controlling the gain of a bipolar transistor by incorporating Ge in the polysilicon emitter. Measured results show that varying the Ge content in the polySiGe from 0 to 33% gives a change in base current of approximately four. The competing influences of the Ge and the interfacial layer at the polySiGe/Si interface are investigated theoretically using an effective surface recombination velocity for the polySiGe emitter. Good agreement between theory and measured results is obtained. When incorporated into a SiGe HBT, the polySiGe emitter will allow the best trade-off between gain and BVCEO to be achieved for a given Ge and B profile in the base.