D. S. Tezcan

High density 20μm pitch CuSn microbump process for high-end 3D applications

In this paper, we present a high yielding 20μm pitch CuSn electroplated microbump flip chip process. The 10μm diameter bumps are organized in an area array, consisting of 440 daisy chains of 1766 bumps each. The 2cm × 2cm flip-chipped dies consist of about 1M bumps in total. The influence of processing materials like seed layer etchants and cleaning agents on the electrical performance of the daisy chains is discussed. Further Ti/Cu versus TiW/Cu seed layers for electroplating are compared. Finally inspection methods for tracing back electrically measured failures are screened.

A New Scaled Through Si Via with Polymer Fill for 3D Wafer Level Packaging

5 0 μ m Over the past 30 years and through scaling, the semiconductor industry has been able to continuously reduce the cost per function while simultaneously increasing the function density. More recently, 3D technologies emerged enabling further reductions in system form factors through stacking and interconnection of (partially) packaged devices. Today, many hand-held products contain stacked chips that are interconnected to each other via the package by means of peripheral wire bonds. The wire bonded 3D-interconnects are limited in terms of density and speed as they exhibit a high inductance. Through-Si vias (TSVs) provide an elegant answer to these limitations since they are naturally much shorter than wire bonds; and hence have better electrical performance. Based on the type of manufacturing platform, IMEC is developing two types of TSVs for different 3D integration schemes [1]. When starting to process 3D interconnects on finished device wafers (CMOS or other), wafer level packaging (WLP) technologies are used. Fig. 1 shows IMECs concept for 3D-WLP technology where thin dies are stacked in a wedding-cake style by means of (micro-)bumps and TSVs.

Development of a Si:As blocked impurity band detector for far IR detection

This paper reports on the fabrication and characterization of a linear array of Blocked Impurity Band (BIB) far infrared detectors and of the related Cryogenic Readout Electronics (CRE). It is part of the ESA DARWIN project which aims at the study of exoplanets by means of null interferometry and requires high performance infrared detector arrays in the 6 18μm range. Si:As BIB detectors have been fabricated on an infrared transparent Silicon substrate enabling backside illumination. The buried contact, the active and the blocking layers are deposited by epitaxy; the doping profile is controlled by adjusting the growth parameters. Access to the buried contact is provided by anisotropic silicon etch of V-grooves in the epi layers. Spray coating of photoresist is used for the lithography of the wafers with high topography. The CRE is composed of an input stage based on an integrating amplifier in AC coupled feedback with selectable integrator capacitors, of a sample and hold stage which provides isolation between input and sampling capacitance, and of an output buffer with multiplexing switch. The readout is optimized for low noise with minimum operating temperature of 4K. Linear arrays made of 42 and 88 detectors and having 30μm pixel pitch with various active areas are fabricated. Detector arrays are coupled to the CRE by Indium bumps using flip-chip technology. Measurements on the readout show reduced noise, good linearity and dynamic range. First detector characterization results are presented.

Monolithic and hybrid backside illuminated active pixel sensor arrays

Two types of backside illuminated CMOS Active Pixel Detectors--optimized for space-borne imaging--have been successfully developed: monolithic and hybrid. The monolithic device is made out of CMOS imager wafers postprocessed to enable backside illumination. The hybrid device consists of a backside thinned and illuminated diode array, hybridized on top of an unthinned CMOS read-out. Using IMECs innovative techniques and capabilities, 2-D arrays with a pitch of 22.5 μm have been realized. Both the hybrid and well as the monolithic APS exhibit high pixel yield, high quantum efficiency (QE), and low dark current. Cross-talk can be reduced to zero in the hybrid sensors utilizing special structures: deep-isolating trenches. These trenches physically separate the pixels and curtail cross-talk. The hybrid imagers are suitable candidates for advanced smart sensors envisioned to be realized as multi-layer 3D integrated systems. The design of both these types of detectors, the key technology steps, the results of the radiometric characterization as well as the intended future developments will be discussed in this paper.

On the processing aspects of high performance hybrid backside illuminated CMOS imagers

In this paper we present a successful integration scheme of a backside (BS) illuminated 1024 × 1024 pixel, 30 µm thin, sensor array that is flip chipped on a read-out IC die with 10 µm diameter indium micro bumps, where the pixel pitch is 22.5 µm. A novel BS alignment strategy to avoid Pyrex glass as a temporary carrier for wafer thinning is described. Pyrex is namely not compatible in a high-end Si process environment due to its fragile and contaminating nature. Further special attention is given to critical steps leading toward high broadband quantum efficiency of 80–90%. It is also shown that through the introduction of high aspect ratio pixel separating trenches, inter-pixel electrical crosstalk can be avoided.

ESH Friendly Solvent for Stripping Positive and Negative Photoresists in 3D-Wafer Level Packaging and 3D-Stacked IC Applications

NMP is a commonly used solvent for removing positive photoresist in 3D applications, especially in electroplating and (micro-) bumping. However, the negative photoresists are more and more preferred in these applications. Unfortunately, NMP is inefficient for negative photoresist and it is not considered in Europe as an ESH solvent anymore. In this paper a comparative study was carried out in order to identify a solvent that is ESH friendly and a one-size-fits-all solution for stripping negative-tone and thick positive-tone photoresist (2-22 μm) for (micro-) bumping, electroplating and TSV etch applications. The study was performed at tool level.

Cold performance tests of blocked-impurity-band Si:As detectors developed for Darwin

We report first results of laboratory tests of Si:As blocked-impurity-band (BIB) mid-infrared (4 to 28 μm) detectors developed by IMEC. These prototypes feature 88 pixels hybridized on an integrated cryogenic readout electronics (CRE). They were developed as part of a technology demonstration program for the future Darwin mission. In order to be able to separate detector and readout effects, a custom build TIA circuitry was used to characterize additional single pixel detectors. We used a newly designed test setup at the MPIA to determine the relative spectral response, the quantum efficiency, and the dark current. All these properties were measured as a function of operating temperature and detector bias. In addition the effects of ionizing radiation on the detector were studied. For determining the relative spectral response we used a dualgrating monochromator and a bolometer with known response that was operated in parallel to the Si:As detectors. The quantum efficiency was measured by using a custom-build high-precision vacuum black body together with cold (T ~ 4K) filters of known (measured) transmission.