Anne Jourdain

Laser Bonding of Glass to Silicon Using Polymer for Microsystems Packaging

Laser joining is a promising technique for wafer-level bonding. It avoids subjecting the complete microelectromechanical system (MEMS) package to a high temperature and/or the high electric field associated with conventional wafer-level bonding processes, using the laser to provide only localized heating. We demonstrate that a benzocyclobutene (BCB) polymer, used as an intermediate bonding layer in the packaging of MEMS devices, can be satisfactorily cured by using laser heating with a substantial reduction of curing time compared with an oven-based process. A glass-on-silicon (Si) cavity bonded with a BCB ring can be produced in a few seconds at a typical laser intensity of 1 W/mm2 resulting in a local temperature of ~300degC. Hermeticity and bond strength tests show that such cavities have similar or better performance than cavities sealed by commercial substrate bonders. The influence of exposure time, laser power, and applied pressure on the degree of cure, bond strength, and hermeticity is investigated. The concept of using a large area uniform laser beam together with a simple mirror mask is tested, demonstrating that such a mask is capable of protecting the center of the cavity from the laser beam; however, to prevent lateral heating via conduction through the Si, a high-conductivity heat sink is required to be in good thermal contact with the rear of the Si.

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.

Failure Mechanisms in MEMS/NEMS Devices

The commercialization of MEMS/NEMS devices is proceeding slower than expected, because the reliability problems of microscopic components differ from macroscopically known behavior. In this chapter, we provide an overview of the state of the art in MEMS/NEMS reliability. We discuss the specific, MEMS-related problems caused by stiction due to surface forces and electric charge. Materials issues such as creep and fatigue are treated as well. Nanoscale wear is covered briefly. MEMS packaging is also discussed, because the reliability of MEMS/NEMS components critically depends on the available protection from the environment.

High density 20μm pitch CuSn microbump process for high-end 3D applications

In this paper, we present a high yielding 20μm pitch CuSn electroplated microbump flip chip process. The 10μm diameter bumps are organized in an area array, consisting of 440 daisy chains of 1766 bumps each. The 2cm × 2cm flip-chipped dies consist of about 1M bumps in total. The influence of processing materials like seed layer etchants and cleaning agents on the electrical performance of the daisy chains is discussed. Further Ti/Cu versus TiW/Cu seed layers for electroplating are compared. Finally inspection methods for tracing back electrically measured failures are screened.

3D Stacking Using Bump-Less Process for Sub 10um Pitch Interconnects

In this paper a bump-less process is introduced in order to further scale down the pitch of microbumps. Electrical resistance measurement, Cross section SEM and mechanical characterizations show successful 3D stacking using proposed method.

Thermal mismatch induced reliability issues for Cu filled through-silicon vias

This paper reports on experiments assessing 3 potential impacts and reliability risks induced by the thermal mismatch between Cu and Si in Cu filled through-silicon via (TSV) integration in 3D technology. The results show that (1) the Cu stress is a higher contributor to stress in the Si than FEOL film edge effects induced by TSV etch; (2) Cu extrusion induced by BEOL processing does not lead to severe delamination/cracking in low-k BEOL layers above the TSV; (3) stress induced at the TSV bottom does not cause visible damage to the liner or backside passivation after wafer thinning.

Characterization of (near) hermetic zero-level packages for MEMS

Zero-level packaging, i.e. the encapsulation of the MEMS device at wafer level, is an essential technique for MEMS miniaturization and cost reduction. A large number of different capping and sealing materials and techniques can be used. However, the testing and qualification of this type of packaging of MEMS devices requires special techniques. A number of conventional and new characterization techniques for mechanical and hermeticity testing are presented, as well as an overview about outgasing measurements and reliability testing.

Development of multi-stack dielectric wafer bonding

We investigate multi-stack dielectric wafer bonding through two integration schemes, which provide different paths to realize vertical integration of multiple device layers. Key process steps are evaluated and optimized to enable void-less bonds at different bonding layers. Meanwhile, issues related to the wafer edge are discovered during the backside processing and the impact is analyzed. Finally, N=4 stacks are successfully demonstrated with high quality interfaces formed by dielectric bonding.

Die to wafer 3D stacking for below 10um pitch microbumps

Processing of bump-less or embedded microbumps is introduced in this paper as an approach which enables scaling microbumps for below 10um pitches. Landing wafer is standard damascene process and in top wafer bumps are embedded in a soft backed polymer. Later during thermo-compression bonding this polymer is cured to bond two chips together. Process flow and results of TC bonding is discussed in this paper.

Impact of backside processing on C-V characteristics of TSV capacitors in 3D stacked IC process flows

In this paper, we describe the importance of carefully selecting the wafer backside processes in 3D stacked IC process flows. In particular, we report on the impact of TSV Via-middle reveal and backside passivation processes on the C-V characteristic of the TSV. The cause of anomalous C-V inversion of the TSV capacitor is explained and a solution is given to avoid this effect.