Ulrich Schwabe

Surface induced latchup in VLSI CMOS circuits

Experimental as well as theoretical results on the latch-up effect in CMOS structures with and without an epitaxial layer are presented. In structures with an epitaxial layer the critical current for latchup firing is two orders of magnitude higher and latchup is essentially surface controlled. The strong surface effect observed is a consequence of the gate influence of surface conduction of the field oxide MOSFETs and on current gains of the bipolar transistors. Latch-up sensitivity can be decreased by increasing p+/p-well and n+/n-well spacing, by decreasing expitaxial layer thickness and by increasing substrate doping. In reducing the lateral dimensions, short-channel effects of the field oxide transistors imply the most severe limitations for latch-up immunity.

Comparison of latch-up in p- and n-well CMOS circuits

The latch-up hardness of p- and n-well CMOS concepts is compared for processes with and without epitaxial layer using electrical and laser-scanning measurements as well as theoretical calculations. It is shown that latch-up hardness does not primarily depend on the parasitic bipolar gain products, which are different for the two concepts, but rather on the shunt resistors in the well and in the substrate. This leads to equal latch-up hardness for n- and p-well concepts without epitaxy. With epitaxy latch-up hardness is strongly increased and is in the case of a p-well by a factor of 5 higher compared with the n-well concept. This is due to the enhanced diffusion of Boron from the p+-substrate in the epitaxial layer.

Surface induced latch-up in VLSI CMOS circuits

Experimental and simulated results of the gate influence on latch-up in CMOS with and without epitaxy are presented. While in CMOS without epitaxy latch-up is bulk initiated, in structures with an epitaxial layer latch-up is essentially surface controlled. The critical latch-up current in this case is two orders of magnitude higher. The strong surface effect observed is a consequence of the gate influence on avalanche breakdown, on surface conduction of the field oxide MOSFETs and on current gains of the bipolar transistors. In reducing the lateral dimensions, short channel effects of the field oxide transistors imply the most severe limitations for latch-up immunity.

Method for manufacturing VLSI complementary MOS field effect transistor circuits in silicon gate technology

Complementary MOS field effect transistor circuits are produced in silicon gate technology, with the method steps up to the structuring of the gate electrode being executed in a known manner. Both source/drain implantations (FIG. 3, 8 and FIG. 5, 10) occur with only one mask (7a). This mask (7a), which is composed of silicon nitride, is utilized for the source/drain implantation 8 of the n-channel transistors (9). The source/drain implantation (10) for the p-channel transistors (11) occurs without a mask and the oxide layer thickness, d6, over the source/drain regions of the n-channel transistors (9) functions as a masking layer. An advantage of this process sequence is that switched capacitor structures (FIG. 6, 5b, 12) can be simultaneously produced whereby the oxide layer thickness, d4, over the polysilicon-1 level (5a, 5b) determines the thickness of the insulating layer, dcox, of the capacitor structures (5b, 12). This technique is useful for manufacturing VLSI CMOS circuits in VLSI technology with and without switched capacitors.

TaSi 2 gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n+-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n+-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.

n-Channel Si-gate process for MNOS EEPROM transistors

Abstract An n -channel Si-gate process has been developed to fabricate MNOS EEPROM transistors and fast logic circuits on one chip. The technology proposed involves low thermal oxidation temperatures ≤900° C after nitride deposition, two LOCOS process steps and application of self-aligned overlapped poly-Si contacts. The MNOS memory transistors obtained have been programmed by ±25 V pulses with a write time of t w = 10 ms and an erase time of t e = 100 ms. The retention data have been found to be dependent on nitride thickness and threshold voltage shift, but independent of channel length and channel doping. For devices with a nitride thickness of 30.5 nm the short-term decay rate of 0.6 V/(decade of time) has been determined. Endurance testing using up to 10 7 pulses of ±25 V, 100 μs corresponding to approx. 10 4 write/erase cycles showed no time dependence for the decay rate over the time of 10 5 min in which retention measurements were made.

N- and P-well optimization for high-speed N-epitaxy CMOS circuits

A double-well n-epi CMOS process was used to investigate the influence of technological parameters relevant to high-speed performance. Dopant concentrations, well depths, channel lengths, and epi-layer thickness have been varied with regard to low propagation delay times measured by three-input NOR/NAND ring oscillators. Parasitic bipolar effects like latchup have been taken into consideration. Ring oscillator circuits designed in general with 3.5-µm design rules and with geometrical gate lengths ≤2 µm exhibited gate delays ≤0.9 ns. The influence of low temperature processing on short-channel and field oxide transistors is discussed.

Reduced n + /p + -spacing with high latchup hardness in self-aligned double well CMOS technology

Latchup in CMOS circuit with an epitaxial layer originates from short channel effects of the parasitic field oxide transistors and from voltage drops on shunt resistances. The short channel behaviour of the field oxide transistors was improved by reducing the p-well depth and modifying the local oxidation step for the well generation. By laser scanning microscope it is shown that for the conventional well latchup firing occurs at the bulges of the well boundary. Using the shallow well the charge compensated region at the well boundary and thereby the latchup sensitive bulges are eliminated. With shallow p-well the shunt resistances are reduced by diminished out-diffusion of the heavily doped n+-substrate and by feasible use of a thinner epi-layer. These measures enable to reduce the critical n+/p+-spacing of adjacent n-and p-channel transistors from 12 µm to 6µm without loosing latchup hardness.

N- and p-well process compatibility in a 1µm-CMOS technology

A 1 µm CMOS concept for 5 V supply-voltage with 22 nm gate oxide and a pure TaSi2gate is presented which allows to realize a n-well- and a p-well-process with widely compatible process flow. Starting in either case from 20 Ωcm epitaxial material on 0.02 Ωcm substrate the process uses equal well depths and identical low well dopant concentrations. Charge carrier mobilities have been found identical in both process concepts. N-channel low-level breakdown voltage is independent of the process concept used. Also independent of the well type the specific junction capacitances inside the well are nearly identical, outside the well typically different. Using ring oscillators with Leff=1.2 µm minimum propagation delays of 120ps for the p-well process and 190ps for the n-well process have been measured.

The influence of temperature on the tolerances of MOS-transistors in a 1 µm technology

In a 1 µm Si-gate technology, channel length and temperature have a strong impact on the electrical device parameters. Experimental data on the influence of the channel length and the temperature on threshold voltage, breakdown voltage and subthreshold currents are presented for different channel dopings and S/D junction depths. The results are discussed with regard to the electrical device tolerances and to limitations in standard Si-gate technologies.