D. Theodore

Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement

We report for the first time PMOS drive current enhancement with in-situ boron doped SiGe incorporation in recessed S/D regions for devices built on thin body SOI substrate. For P-channel PD-SOI devices with 450 A silicon on insulator and 38nm gate length, 35% linear drain current enhancement and 20% saturation drain current improvement have been achieved with this approach. Device integration and performance improvement are discussed below.

Metrology Challenges for 45-nm Strained-Si Device Technology

The semiconductor industry has maintained its historical exponential improvement in performance by aggressively scaling transistor dimensions. However, as devices approach sub-100-nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limitations imposed by existing materials. For example, as power supply voltages continue to decrease with successive scaling, enhancing carrier mobility using biaxially tensile-stressed Si on relaxed SiGe on SOI and on bulk substrates has become a viable option to sustain continual drive current increase without traditional scaling. Although the addition of strained-Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are new device and process integration challenges, wafer quality monitoring demands, and stringent requirements for film morphology and strain uniformity, imposing new demands on material characterization. Material requirements for strained-Si CMOS devices include having uniform SiGe thickness, Ge composition, and strain distribution. These are required to maintain uniform device performance as well as low defect density for high minority carrier lifetimes and transconductance, as well as low surface roughness to minimize the impact of interface scattering on carrier mobilities. The parameters of interest in strained-Si CMOS technology include SiGe and Si channel thickness, Ge composition, strain, dislocation density, interface quality, and roughness. Nondestructive inline metrology techniques include spectroscopic ellipsometry for film thickness and Ge composition, X-ray reflectivity for thickness, density, and roughness measurements, X-ray fluorescence for Ge composition, UV-Raman spectroscopy for channel strain characterization, IR photoluminescence for defect detection, and X-ray diffraction for both Ge content and strain measurement. While most of these techniques are well established in the semiconductor industry, some will require development for application to volume manufacturing. This paper will focus on various metrology approaches used in strained-Si CMOS devices

Metrology Challenges for 45 nm Strained‐Si Devices

The semiconductor industry has sustained its historical exponential performance gains by aggressively scaling transistor dimensions. However, as devices approach sub‐100 nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limits imposed by existing materials. For example, as power supply voltages continue to decrease with successive scaling, enhanced carrier mobility using biaxially tensile‐strained‐Si on SOI or on bulk substrates have become viable options to sustain continual drive current increases without traditional scaling. Although the addition of strained‐Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are new device and process integration challenges, wafer quality monitoring demands, and stringent requirements for film morphology and strain uniformity, imposing new demands on material characterization. Material requirements for strained‐Si CMOS devices include homogeneous Si or...

An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing

We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (Csub) epitaxial Si:C and laser spike annealing (LSA) for increased Csub incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% Csub and 60% Rch reduction for 2.2% Csub are demonstrated.

Dual Silicide SOI CMOS Integration with Low-Resistance PtSi PMOS Contacts

We demonstrate a dual silicide integration on a SOI CMOS platform with robust low-resistance PtSi PMOS contacts. Compared to NiSi, the specific contact resistivity is reduced in PtSi contacts to p-type Si and increased in contacts to n-type Si. PMOS linear and saturation drive current enhancements of 6% and 9%, respectively, were achieved with PtSi relative to baseline NiSi source/drain contacts.

Metrology Of Silicide Contacts For Future CMOS

Silicide materials (NiSi, CoSi2, TiSi2, etc) are used to form low‐resistance contacts between the back‐end (W plugs and Cu interconnects) and front‐end portions (silicon source, drain, and gate regions) of integrated CMOS circuits. At the 65 nm node, a transition from CoSi2 to NiSi was necessary because of the unique capability of NiSi to form narrow silicide nanowires on active (monocrystalline) and gate (polycrystalline) lines. Like its predecessors TiSi2 and CoSi2, NiSi is a mid‐gap silicide, i.e., the Fermi level of the NiSi metal is pinned half‐way between the conduction and valence band edges in silicon. This leads to a Schottky barrier between the silicide and silicon source‐drain regions, which creates undesirable parasitic resistances. For future CMOS generations, band‐edge silicides, such as PtSi for contacts to p‐type or rare earth silicides for contacts to n‐type Si will be needed. This paper reviews metrology and characterization techniques for NiSi process control for development and manufac...

Uniaxial and Biaxial Strain for CMOS Performance Enhancement

Uniaxial stressors have been mainly employed for boosting PMOS performance, while it is more difficult to increase NMOS performance using tensile stressors. This results in changing the n:p ratio, which requires circuit layout changes. Enhancing both NMOS and PMOS performance to retain the same n:p ratio is desirable. Interactions between biaxial lattice strain, uniaxial relaxation, process-induced stressor and channel orientation have been optimized to achieve the desired stress configurations for enhancing both short-channel SSOI NMOS and PMOS devices

Limits of Optical and X‐ray Metrology Applied to Thin Gate Dielectrics

We analyze the limits of optical and x‐ray metrology techniques (spectroscopic ellipsometry, x‐ray reflectivity, and powder x‐ray diffraction) applied to thin films in microelectronics, especially metal oxides used as gate dielectrics. By tilting the substrate from the symmetric scattering geometry, we can enhance the sensitivity of powder diffraction and detect the tetragonal (011) Bragg peak from a 30 A thick HfO2 layer on Si. We have calculated the Bragg peak positions and intensities of tetragonal hafnia. Vacuum‐ultraviolet spectroscopic ellipsometry and grazing‐incidence x‐ray reflectivity spectra for 50 to 200 A thick HfO2 layers on Si (001) can be described by a model, which consists of only a single (metal oxide) layer on the Si substrate. These techniques, within the scope of our work, are unable to determine the thickness of the interfacial oxide layer between the metal oxide and the substrate. A method to determine the optical properties (complex dielectric function) of thin insulating layers o...

Transmission Electron Microscopy Studies of Strained Si CMOS

In this paper, various types of defects (both threading dislocation and misfit dislocations) in strained Si (sSi) have been analyzed by transmission electron microscopy (TEM). Germanium upper-diffusion has been studied by scanning transmission electron microscopy (STEM) for strained Si on SiGe/SOI. SGOI-devices processed using an optimized thermal budget show minimal Ge diffusion and minimal process related defects. Correlation between the device performance (such as leakage current and reliability) and structural information found in TEM has been established.