D.Y. Jeon

Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay

We report a room temperature, 0.1 /spl mu/m CMOS technology on bulk Si substrates that delivers a record ring-oscillator gate delay of 11.8 psec at 2.5 V. Frequency dividers at 2.0 V operate with input frequencies exceeding 8.5 GHz. Feature sizes obey g-line lithography design rules except at the gate level. The high speed CMOS performance and the good subthreshold and drain characteristics for both NMOS and PMOS devices are obtained through the implementation of vertical doping engineering and the reduction of parasitics.<<ETX>>

Scaling the Si metal‐oxide‐semiconductor field‐effect transistor into the 0.1‐μm regime using vertical doping engineering

Conventional scaling of the Si MOSFET into the deep submicron regime requires high substrate doping levels. This extracts a severe speed penalty, if lower standby power consumption (i.e., good subthreshold behavior) is to be maintained. We explore the scaling of fully depleted silicon‐on‐insulator (SOI) structures, and show, both analytically and by numerical simulation, how the horizontal leakage is controlled by vertical doping engineering. Our analysis allows different structures to be evaluated in terms of a natural length scale indicating good subthreshold behavior. Finally, we describe how retrograde doping may be used to mimic the SOI concept in bulk Si. Our results show good subthreshold behavior in the deep submicron regime can be achieved without large junction capacitance, high threshold voltage, or heavy channel doping.

High performance 0.1- mu m room temperature Si MOSFETs

The design and implementation of 0.15- mu m-channel N-MOSFETs with very high current drive and good short channel behavior at room temperature are discussed. Measured subthreshold characteristics show a slope of 84 mV/dec and a shift for 75 mV for Delta V/sub ds/=1 V. A peak g/sub m/ of 570 mS/mm was recorded, leading to a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz. Key process steps include the formation of 40-AA gate oxides and sub-500-AA junctions. Vertical doping engineering was used to minimize doping at the surface and beneath the junctions, while maintaining good turn-off characteristics.<<ETX>>

89-GHz f/sub T/ room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 AA, and a channel length of 0.15 mu m. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region.<<ETX>>

An ultra high speed ECL-bipolar CMOS technology with silicon fillet self-aligned contacts

An ultra-high-speed half-micron non-overlapped super self-aligned BiCMOS technology that uses a silicon fillet self-aligned contact technology (SIFT) for both bipolar and MOS transistors is discussed. The SIFT process reduces the device capacitances and series resistances by minimizing the diffusion region area as well as the polysilicon electrode area. Deep trench isolation for bipolar transistors allows the device area to be much reduced for VLSI applications. The ECL gate delay is demonstrated to be 31 ps for devices with emitter polysilicon widths of 0.6 mu m. The CMOS ring oscillator gate delays are 58 ps for 0.5- mu m gate length and 67 ps for 0.6- mu m gate length at 5 V.<<ETX>>

Performance optimization of a high speed super self-aligned BiCMOS technology

The authors present the process optimization and device characteristics of a half-micron super self-aligned BiCMOS technology. With a new emitter/base process in their BiCMOS flow, bipolar transistor power gain cutoff frequency, f/sub max/, has been increased from 25.9 GHz to 33.5 GHz. Since all the process parameters related to CMOS are kept constant, high speed CMOS circuit operation is maintained without compromise. The measured nominal CMOS gate delay with a gate length of 0.5 mu m is 47 psec at 5V and 54 psec at 3.3V.<<ETX>>

Microstructure of the emitter polycrystalline silicon/silicon interface in bipolar transistors after rapid thermal annealing

We use high‐resolution transmission electron microscopy to determine the microstructure of the emitter polycrystalline (poly) Si/Si interface of real bipolar transistor devices after rapid thermal annealing. Our results quantify the size and density of interfacial oxide voids (pinholes), the areal fraction of the interface covered with voids, and the amount of epitaxial regrowth after annealing in the range 1000–1150 °C. Correlation of these results with the characteristics of the devices shows that the most dramatic electrical changes occur before 2% of the poly‐Si/Si interfacial area is covered with oxide voids.