Kwing F. Lee

Scaling the Si MOSFET: from bulk to SOI to bulk

Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >

Impact of distributed gate resistance on the performance of MOS devices

This paper describes the impact of gate resistance on cut-off frequency (f/sub T/), maximum frequency of oscillation (f/sub max/), thermal noise, and time response of wide MOS devices with deep submicron channel lengths. The value of f/sub T/ is proven to be independent of gate resistance even for distributed structures. An exact relation for f/sub max/ is derived and it is shown that, to predict f/sub max/, thermal noise, and time response, the distributed gate resistance can be divided by a factor of 3 and lumped into a single resistor in series with the gate terminal. >

Design of high-speed, low-power frequency dividers and phase-locked loops in deep submicron CMOS

Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless products. This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phase-locked loop, fabricated in a partially scaled 0.1 /spl mu/m CMOS technology. Configured as a master-slave circuit, the divider achieves a maximum speed of 13.4 GHz with a power dissipation of 28 mW. The phase-locked loop employs a current-controlled oscillator and a symmetric mixer to operate at 3 GHz with a tracking range of /spl plusmn/320 MHz, an rms jitter of 2.5 ps, and a phase noise of -100 dBc/Hz while dissipating 25 mW. >

Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay

We report a room temperature, 0.1 /spl mu/m CMOS technology on bulk Si substrates that delivers a record ring-oscillator gate delay of 11.8 psec at 2.5 V. Frequency dividers at 2.0 V operate with input frequencies exceeding 8.5 GHz. Feature sizes obey g-line lithography design rules except at the gate level. The high speed CMOS performance and the good subthreshold and drain characteristics for both NMOS and PMOS devices are obtained through the implementation of vertical doping engineering and the reduction of parasitics.<<ETX>>

A 13.4-GHz CMOS frequency divider

This paper describes the design ofa 13.4 GHz 1/2-frequency divider fabricated in a partially-scaled 0.1 /spl mu/m bulk CMOS technology. The circuit design is heavily influenced by the device structures and layout rules. To reduce both fabrication cost and turnaround time, the CMOS process scales only channel length to 0.1 /spl mu/m and gate oxide to 40 /spl Aring/. Design rules for other dimensions correspond to a 1 /spl mu/m technology, yielding a minimum source/drain area of 2.2 /spl times/2.2 /spl mu/m/sup 2/. Thus the contribution of the source/drain junction capacitance is substantial, severely limiting speed. The divider described employs the following techniques to improve the speed: 1) nMOSFETs for sensing and regeneration and pMOSFETs for pull-up, 2) no stacked devices and pass gates, 3) ring-shaped geometry for all transistors.<<ETX>>

Scaling the Si metal‐oxide‐semiconductor field‐effect transistor into the 0.1‐μm regime using vertical doping engineering

Conventional scaling of the Si MOSFET into the deep submicron regime requires high substrate doping levels. This extracts a severe speed penalty, if lower standby power consumption (i.e., good subthreshold behavior) is to be maintained. We explore the scaling of fully depleted silicon‐on‐insulator (SOI) structures, and show, both analytically and by numerical simulation, how the horizontal leakage is controlled by vertical doping engineering. Our analysis allows different structures to be evaluated in terms of a natural length scale indicating good subthreshold behavior. Finally, we describe how retrograde doping may be used to mimic the SOI concept in bulk Si. Our results show good subthreshold behavior in the deep submicron regime can be achieved without large junction capacitance, high threshold voltage, or heavy channel doping.

High performance 0.1- mu m room temperature Si MOSFETs

The design and implementation of 0.15- mu m-channel N-MOSFETs with very high current drive and good short channel behavior at room temperature are discussed. Measured subthreshold characteristics show a slope of 84 mV/dec and a shift for 75 mV for Delta V/sub ds/=1 V. A peak g/sub m/ of 570 mS/mm was recorded, leading to a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz. Key process steps include the formation of 40-AA gate oxides and sub-500-AA junctions. Vertical doping engineering was used to minimize doping at the surface and beneath the junctions, while maintaining good turn-off characteristics.<<ETX>>

Non-overlapping super self-aligned BiCMOS with 87 ps low power ECL

It is demonstrated that high-speed bipolar and CMOS processes can be merged without compromise on either device. A NOVA (nonoverlapping super self-aligned) structure with an advanced epi/isolation process that reduces parasitic capacitances and resistances is reported. The scheme combines lateral autodoping free epi deposition with a novel fully recessed oxide process. This approach significantly simplifies the isolation process and is an important factor in achieving high speed with a conservative 1.5- mu m design rule. A high-speed frequency divider, a multiplexer, and a demultiplexer operating up to 4.1 GHz, 5.5 Gb/s, and 6.2 Gb/s, respectively, have been fabricated. The results show that NOVA BiCMOS is suitable for Gb/s digital VLSI application.<<ETX>>

89-GHz f/sub T/ room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 AA, and a channel length of 0.15 mu m. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region.<<ETX>>

A 3-ghz 25-mw Cmos Phase-locked Loop

The demand for high-speed, low-power communication circuits has dramatically grown over the past few years. Potential markets from powerful personal communicators to wireless ATM systems have stimulated great effort in reducing the supply voltage and power dissipation of gigahertz circuits. In this respect, deep submicron CMOS technologies have become contenders to 111-V and silicon bipolar devices because they offer the speed, density, and power required for such applications. This paper describes the design of a 3-GHz phase-locked loop (PLL) fabricated in a partially-scaled 0.1-pm bulk CMOS technology [l]. The circuit employs a number of techniques to allow operation from a low supply voltage and overcome the limitations due to device layout rules described below. In order to improve the yield and reduce the turnaround time and cost, the CMOS process used here scales only the channel