R.G. Swartz

High-speed, burst-mode, packet-capable optical receiver and instantaneous clock recovery for optical bus operation

This paper describes an enhanced performance version of a high-speed burst-mode compatible optical receiver and its application to 622-Mb/s optical bus operation in conjunction with an instantaneous clock recovery scheme. The receiver is fabricated in a 12 GHz f/sub t/ silicon bipolar technology and consists of a differential transimpedance amplifier with an auto-threshold level controller and a high-speed quantizer. Using an InGaAs avalanche photodiode, the typical burst mode sensitivity is around /spl minus/34 dBm (10/sup /spl minus/9/ BER) at bit rates up to 1.5 Gb/s with a dynamic range of 26 db for both pseudorandom and burst signals. The results using a laser beam modulated by a high-speed external modulator indicate that the receiver can be operated at bit rates higher than 2 Gb/s. With a worst-case self-resetting time >

Design techniques for low-voltage high-speed digital bipolar circuits

This paper describes design techniques for multigigahertz digital bipolar circuits with supply voltages as low as 1.5 V. Examples include a 2/1 multiplexer operating at 1 Gb/s with 1.2 mW power dissipation, a D-latch achieving a maximum speed of 2.2 GHz while dissipating 1.4 mW, two exclusive-OR gates with a delay less than 200 ps and power dissipation of 1.3 mW, and a buffer/level shifter having a delay of 165 ps while dissipating 1.4 mW. The prototypes have been fabricated in a 1.5-/spl mu/m 12-GHz bipolar technology. Simulations on benchmarks such as frequency dividers and line drivers indicate that, for a 1.5-V supply, the proposed circuits achieve higher speed than their CMOS counterparts designed in a 0.5-/spl mu/m CMOS process with zero threshold voltage. >

Integrated silicon-PVF 2 acoustic transducer arrays

A new type of transducer array has been designed which employs a piezoelectric polymer, polyvinylidene fluoride (PVF2), as the sensing material. Acoustic properties possessed by this piezoelectric polymer provide a reasonable match to those of the human body making it very attractive for medical ultrasonic imaging systems. Using planar integrated-circuit (IC) technology, an array of MOSFET input amplifiers is fabricated on a silicon wafer. A single sheet of PVF2is bonded to the surface of the wafer. Spatially varying acoustic signals detected by the PVF2are converted to corresponding charge distributions on the underlying array of amplifiers. A linear 34-element receiving transducer array has been built and evaulated. Array transverse dimensions are 14.7 × 9 mm, so that the silicon die area is approximately 1.32 cm2. Individual transducers are 0.42 × 9 mm corresponding to the requirements of a particular system. Associated with each of the 34 transducers is a DMOS-bipolar cascode amplifier. Experimentally measured transducer impulse response decays 20 dB in two cycles. Using silicon technology, arrays of almost arbitrary size and complexity appear feasible.

Burst-mode compatible optical receiver with a large dynamic range

A description is given of the characteristics and performance of a burst-mode receiver for optical data communication that employs a differential transimpedance amplifier and an auto-threshold-tracking level control circuit in the preamplifier. The differential outputs of the preamplifier are DC-coupled to the decision circuit to achieve burst-mode compatibility. The receiver was assembled in a compact dual inline package with an optical connector. The typical sensitivities are around -31.5 and -29.5 dBm/Av at 200 Mb/s (at a bit error rate of 10/sup -9/) for pseudorandom and burst-mode signals, respectively, with dynamic ranges of 27.5 and 25.5 dB, respectively. The operating bit rate ranges from DC to 500 Mb/s, and the differential outputs are true ECL (emitter-coupled logic). >

DC-1 Gb/s burst-mode compatible receiver for optical bus applications

The characteristics and performance of a high-speed, burst-mode compatible receiver for optical bus or packet communications are described. It employs an Si bipolar differential transimpedance amplifier, an auto-threshold tracking level control circuit, and a DC-coupled decision circuit (ECL compatible quantizer). To cope with intermittent data packets, the threshold control circuit can capture data amplitude and set the logic threshold in about 1 ns. Using an avalanche photodiode, the typical receiver sensitivity is -37.5 dBm (10/sup -9/ BER) at bit rates up to 900 Mb/s, with a dynamic range of 23 dB for both pseudorandom and burst-mode signals. At 1 Gb/s, the sensitivity is -35 dBm. With a worst-case reset time >

High performance 0.1- mu m room temperature Si MOSFETs

The design and implementation of 0.15- mu m-channel N-MOSFETs with very high current drive and good short channel behavior at room temperature are discussed. Measured subthreshold characteristics show a slope of 84 mV/dec and a shift for 75 mV for Delta V/sub ds/=1 V. A peak g/sub m/ of 570 mS/mm was recorded, leading to a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz. Key process steps include the formation of 40-AA gate oxides and sub-500-AA junctions. Vertical doping engineering was used to minimize doping at the surface and beneath the junctions, while maintaining good turn-off characteristics.<<ETX>>

89-GHz f/sub T/ room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 AA, and a channel length of 0.15 mu m. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region.<<ETX>>

A technique for rapidly alternating boron and arsenic doping in ion‐implanted silicon molecular beam epitaxy

This letter reports the use of boron ion implantation doping during simultaneous growth of silicon molecular beam epitaxy. It describes further a technique for epitaxial growth of abrupt silicon p‐n junctions by rapid changeover during growth between boron and arsenic ion beams. This is expected to be of importance in a variety of applications, including, for example, high speed bipolar junction transistors.

Stabilization and optimum biasing of dynamic‐single‐mode coupled‐cavity lasers

Stabilization and control of coupled‐cavity lasers are considered. Constant output power plots on the I1 vs I2 plane determine optimum dc bias points and how the rf modulation should be applied. A double feedback‐loop control circuit provides stable, single‐mode operation over wide ranges of temperature and power under modulation. Experiments demonstrate ≥24 dB of spurious mode suppression under almost complete on/off high‐speed modulation over >15 °C.

A high performance super self-aligned 3 V/5 V BiCMOS technology with extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 /spl mu/m design rules (0.5 /spl mu/m as one nesting tolerance) has achieved f/sub l/ and f/sub max/ for npn bipolar (A/sub e/=1/spl times/2 /spl mu/m/sup 2/) of 23 GHz and 24 GHz at V/sub ce/=3 V, respectively, with BV/sub ceospl ges/5.5 volts, and /spl beta/V/sub A/ product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A/sub e/=1/spl times/2 /spl mu/m/sup 2/; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 /spl Aring/, L/sub eff/=0.6 /spl mu/m; V/sub th,nch/=0.45 V; V/sub th,pch/=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 /spl mu/m; gate L/sub eff/=0.7 /spl mu/m) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW. >