M.D. Morris

Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay

We report a room temperature, 0.1 /spl mu/m CMOS technology on bulk Si substrates that delivers a record ring-oscillator gate delay of 11.8 psec at 2.5 V. Frequency dividers at 2.0 V operate with input frequencies exceeding 8.5 GHz. Feature sizes obey g-line lithography design rules except at the gate level. The high speed CMOS performance and the good subthreshold and drain characteristics for both NMOS and PMOS devices are obtained through the implementation of vertical doping engineering and the reduction of parasitics.<<ETX>>

High performance 0.1- mu m room temperature Si MOSFETs

The design and implementation of 0.15- mu m-channel N-MOSFETs with very high current drive and good short channel behavior at room temperature are discussed. Measured subthreshold characteristics show a slope of 84 mV/dec and a shift for 75 mV for Delta V/sub ds/=1 V. A peak g/sub m/ of 570 mS/mm was recorded, leading to a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz. Key process steps include the formation of 40-AA gate oxides and sub-500-AA junctions. Vertical doping engineering was used to minimize doping at the surface and beneath the junctions, while maintaining good turn-off characteristics.<<ETX>>

Non-overlapping super self-aligned BiCMOS with 87 ps low power ECL

It is demonstrated that high-speed bipolar and CMOS processes can be merged without compromise on either device. A NOVA (nonoverlapping super self-aligned) structure with an advanced epi/isolation process that reduces parasitic capacitances and resistances is reported. The scheme combines lateral autodoping free epi deposition with a novel fully recessed oxide process. This approach significantly simplifies the isolation process and is an important factor in achieving high speed with a conservative 1.5- mu m design rule. A high-speed frequency divider, a multiplexer, and a demultiplexer operating up to 4.1 GHz, 5.5 Gb/s, and 6.2 Gb/s, respectively, have been fabricated. The results show that NOVA BiCMOS is suitable for Gb/s digital VLSI application.<<ETX>>

89-GHz f/sub T/ room-temperature silicon MOSFETs

The authors report the implementation of deep-submicrometer Si MOSFETs that at room temperature have a unity-current-gain cutoff frequency (f/sub T/) of 89 GHz, for a drain-to-source bias of 1.5 V, a gate-to-source bias of 1 V, a gate oxide thickness of 40 AA, and a channel length of 0.15 mu m. The fabrication procedure is mostly conventional, except for the e-beam defined gates. The speed performance is achieved through an intrinsic transit time of only 1.8 ps across the active device region.<<ETX>>

An ultra high speed ECL-bipolar CMOS technology with silicon fillet self-aligned contacts

An ultra-high-speed half-micron non-overlapped super self-aligned BiCMOS technology that uses a silicon fillet self-aligned contact technology (SIFT) for both bipolar and MOS transistors is discussed. The SIFT process reduces the device capacitances and series resistances by minimizing the diffusion region area as well as the polysilicon electrode area. Deep trench isolation for bipolar transistors allows the device area to be much reduced for VLSI applications. The ECL gate delay is demonstrated to be 31 ps for devices with emitter polysilicon widths of 0.6 mu m. The CMOS ring oscillator gate delays are 58 ps for 0.5- mu m gate length and 67 ps for 0.6- mu m gate length at 5 V.<<ETX>>

The design and characterization of nonoverlapping super self-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L/sub eff/=1.1 mu m and W/sub n//W/sub p/=10 mu m/10 mu m exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f/sub T/, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated. >

Nonoverlapping super self-aligned device structure for high-performance VLSI

The nonoverlapping super self-aligned structure (NOVA) is reported. Because of its nonoverlapping nature, this structure can be applied equally well to bipolar, CMOS, or BiCMOS processes. This structure effectively minimizes parasitic capacitance and resistance for both the MOS and bipolar devices. CMOS and bipolar devices are integrated into a high-performance BiCMOS technology. CMOS and emitter-coupled logic (ECL) ring oscillators with 1.5- mu m lithography are reported to have delays of 128 and 87 ps/stage, respectively.<<ETX>>

Suppression of lateral autodoping from arsenic buried layer by selective epitaxy capping

An effective way to suppress lateral autodoping from the heavily arsenic-doped buried layer during silicon epitaxy is described. By using this simple technique, collector-substrate capacitance (C/sub cs/) is minimized. This process is ideal for high-speed BiCMOS and bipolar technology. A thin epilayer is first grown selectively on the buried layer. This selectively grown film suppresses the release of arsenic during the subsequent epi growth. High-performance bipolar devices have been fabricated in this epi material. Electrical measurements indicate that the crystalline quality is excellent.<<ETX>>

Lateral Autodoping Suppression by Selective Epitaxy Capping and Its Application in High Speed BiCMOS

fabrication. Other advanced technique like trench isolation may be considered. Trench isolation is, however, involved and expensive. A simple solution is to apply the recently reported selective epi growth (SEG)4-6). Fig.2 illustrates the process sequence. Single crystal silicon is selectively grown inside oxide windows. The highly doped buried layer is now capped. In addition, the oxide protects the off-buried layer region from the arsenic contamination. Subsequently, the oxide mask is removed and an epitaxy layer of desired doping is deposited. Lateral autodoping can be reduced by 2-3 orders of magnitude while maintaining a low arsenic buried layer sheet

Performance optimization of a high speed super self-aligned BiCMOS technology

The authors present the process optimization and device characteristics of a half-micron super self-aligned BiCMOS technology. With a new emitter/base process in their BiCMOS flow, bipolar transistor power gain cutoff frequency, f/sub max/, has been increased from 25.9 GHz to 33.5 GHz. Since all the process parameters related to CMOS are kept constant, high speed CMOS circuit operation is maintained without compromise. The measured nominal CMOS gate delay with a gate length of 0.5 mu m is 47 psec at 5V and 54 psec at 3.3V.<<ETX>>