Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Dae-youn Kim is active.

Publication


Featured researches published by Dae-youn Kim.


symposium on vlsi technology | 2005

S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

Ji-Hui Kim; Hansu Oh; D.S. Woo; Y.S. Lee; D. H. Kim; Sung-Gi Kim; G.W. Ha; H.J. Kim; N.J. Kang; J.M. Park; Young-Nam Hwang; Dae-youn Kim; Byung-lyul Park; M. Huh; B.H. Lee; S.B. Kim; Myoung-kwan Cho; Min-wook Jung; Young-Ran Kim; C. Jin; Dong-woon Shin; Myoungseob Shim; C.S. Lee; Woon-kyung Lee; Jong-Dae Park; G.Y. Jin; Young-rae Park; Kinam Kim

For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.


symposium on vlsi technology | 2005

The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

Jung-Geun Kim; D.S. Woo; Hansu Oh; H.J. Kim; Sung-Gi Kim; Byung-lyul Park; Jin-Hyoung Kwon; Myoungseob Shim; G.W. Ha; Jai-Hyuk Song; N.J. Kang; J.M. Park; Ho Kyong Hwang; S.S. Song; Young-Nam Hwang; Dae-youn Kim; D. H. Kim; M. Huh; D.H. Han; C.S. Lee; Seok-Han Park; Yongho Kim; Y.S. Lee; Min-wook Jung; Young-Ran Kim; B.H. Lee; Myung-Haing Cho; W.T. Choi; Hyun-Su Kim; G.Y. Jin

The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented. The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.


european solid state device research conference | 2005

High-density low-power-operating DRAM device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyond

Hyeok-Sang Oh; Jun-Hyung Kim; Jung-hyeon Kim; S.G. Park; D. H. Kim; Sung-Gi Kim; D.S. Woo; Y.S. Lee; G.W. Ha; J.M. Park; N.J. Kang; Hui-jung Kim; J.S. Hwang; Bong-Hyun Kim; Dae-youn Kim; Young-Seung Cho; J.K. Choi; B.H. Lee; S.B. Kim; Myoung-kwan Cho; Yihwan Kim; Jung-Hwan Choi; Dong-woon Shin; Myoungseob Shim; W.T. Choi; G.P. Lee; Young-rae Park; Wonseok Lee; Byung-Il Ryu

For the first time, the DRAM device composed of 6F/sup 2/ open-bit-line memory cell with 80nm feature size is developed. Adopting 6F/sup 2/ scheme instead of customary 8F/sup 2/ scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F/sup 2/ accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F/sup 2/, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell V/sub th/ so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (sphere-shaped-recess-channel-array transistor) is introduced. It is the improved scheme of RCAT used in 8F/sup 2/ scheme. By adopting S-RCAT, V/sub th/ can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.


symposium on vlsi technology | 2004

Novel robust cell capacitor (Leaning Exterminated Ring type Insulator) and new storage node contact (Top Spacer Contract) for 70nm DRAM technology and beyond

J.M. Park; Young-Nam Hwang; Dong-woon Shin; M. Huh; D. H. Kim; Ho Kyong Hwang; Hansu Oh; Jai-Hyuk Song; N.J. Kang; B.H. Lee; C.J. Yun; Myoungseob Shim; Sung-Gi Kim; Jung-Geun Kim; Jin-Hyoung Kwon; Byung-lyul Park; J.W. Lee; Dae-youn Kim; Myoung-kwan Cho; M.Y. Jeong; H.J. Kim; Hyun-Su Kim; G.Y. Jin; Yeonsang Park; Kinam Kim

For the first time, novel robust capacitor (Leaning exterminated Ring type Insulator - LERI) and new storage node (SN) contact process (Top Spacer Contact - TSC) are successfully developed with 82nm feature size. These novel processes drastically improved electrical characteristics such as cell capacitance, parasitic bit line capacitance and cell contact resistance, compared to a conventional process. The most pronounced effect using the LERI in COB structure is to greatly improve cell capacitance without twin bit failure. In addition, the TSC technology has an ability to remove a critical ArF lithography. By using the LERI and TSC processes in 82nm 512M DDR DRAM, the cell capacitance of 32fF/cell is achieved with Toxeq of 2.3nm and the parasitic bit line capacitance is reduced by 20%, resulted in great improvement of tRCD (1.5ns).


symposium on vlsi technology | 2003

Novel plasma enhanced atomic layer deposition technology for high-k capacitor with EOT of 8 /spl Aring/ on conventional metal electrode

Seok-jun Won; Yong-kuk Jeong; Dae-jin Kwon; Moon-han Park; Ho-Kyu Kang; Kwang-Pyuk Suh; Hong-ki Kim; Jae-Hwan Ka; Kwan-Young Yun; Duck-Hyung Lee; Dae-youn Kim; Yong-Min Yoo; Choon-Soo Lee

We have developed a plasma enhanced atomic layer deposition(PEALD) technology for high-k dielectrics such as Al/sub 2/O/sub 3/,Ta/sub 2/O/sub 5/ and HfO/sub 2/. Film quality and throughput of PEALD are far superior to that of ALD which has been spotlighted as a deposition technology for next generation semiconductor devices. We have obtained a extremely low equivalent oxide thickness(EOT) of 8 /spl Aring/ from HfO/sub 2/ film, which has not been reported in conventional metal-based memory capacitors up to now. It was confirmed that PEALD-Al/sub 2/O/sub 3/ and Ta/sub 2/O/sub 5/ films are superior to those using any other deposition techniques and very useful as System-on-Chip(SoC) capacitors.


Archive | 2010

Method of Forming Metal Oxide and Apparatus for Performing the Same

Seok-jun Won; Yong-Min Yoo; Min-Woo Song; Dae-youn Kim; Young Hoon Kim; Weon-Hong Kim; Jung-min Park; Sun-mi Song


Archive | 2012

APPARATUS INCLUDING 4-WAY VALVE FOR FABRICATING SEMICONDUCTOR DEVICE, METHOD OF CONTROLLING VALVE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE APPARATUS

Seok-jun Won; Yong-Min Yoo; Dae-youn Kim; Young Hoon Kim; Dae-jin Kwon; Weon-Hong Kim


Journal of the Korean Physical Society | 2004

Raised source-drain transistors in a cell and support area with co-silicide for 88-nm DRAM technology and beyond

Youngmin Choi; Jung-Geun Kim; M.Y. Jeong; H.J. Kim; Hyun-Su Kim; Sung-Gi Kim; Byung-lyul Park; I. B. Chung; Dae-youn Kim; J.W. Lee; Ho Kyong Hwang; Young-Nam Hwang; D.S. Hwang; Joonmin Park; Mi-Jeong Jo; D. H. Kim; Namwoo Kang; Young-rae Park; Kinam Kim


Archive | 2007

Method of forming metal oxide

Seok-jun Won; Yong-Min Yoo; Min-Woo Song; Dae-youn Kim; Young Hoon Kim; Weon-Hong Kim; Jung-min Park; Sun-mi Song


Archive | 2006

Vorrichtung und Verfahren zur Herstellung eines Halbleiterbauelements

Dae-youn Kim; Weon-Hong Kim; Young Hoon Kim; Dae-jin Suwon Kwon; Seok-Jun Won; Yong-Min Yoo

Collaboration


Dive into the Dae-youn Kim's collaboration.

Researchain Logo
Decentralizing Knowledge