Myoungseob Shim

S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.

The excellent scalability of the RCAT (recess-channel-array-transistor) technology for sub-70nm DRAM feature size and beyond

The technology innovation for extending the RCAT structure to the sub-70nm DRAM is presented. The new technology overcomes the problems induced by shrinkage of the RCAT structure and meets the requirements for the next generation DRAMs, such as high speed and low power performance. The technology roadmap down to the 50nm DRAM feature size of the RCAT development is presented.

High-density low-power-operating DRAM device adopting 6F/sup 2/ cell scheme with novel S-RCAT structure on 80nm feature size and beyond

For the first time, the DRAM device composed of 6F/sup 2/ open-bit-line memory cell with 80nm feature size is developed. Adopting 6F/sup 2/ scheme instead of customary 8F/sup 2/ scheme made it possible to reduce chip size by up to nearly 20%. However, converting the cell scheme to 6F/sup 2/ accompanies some difficulties such as decrease of the cell capacitance, and more compact core layout. To overcome this strict obstacles which are originally stemming from the conversion of cell scheme to 6F/sup 2/, TIT structure with AHO (AfO/AlO/AfO) is adopted for higher cell capacitance, and bar-type contact is adopted for adjusting to compact core layout. Moreover, to lower cell V/sub th/ so far as suitable for characteristic of low power operation, the novel concept, S-RCAT (sphere-shaped-recess-channel-array transistor) is introduced. It is the improved scheme of RCAT used in 8F/sup 2/ scheme. By adopting S-RCAT, V/sub th/ can be lowered, SW, DIBL are improved. Additionally, data retention time characteristic can be improved.

Novel robust cell capacitor (Leaning Exterminated Ring type Insulator) and new storage node contact (Top Spacer Contract) for 70nm DRAM technology and beyond

For the first time, novel robust capacitor (Leaning exterminated Ring type Insulator - LERI) and new storage node (SN) contact process (Top Spacer Contact - TSC) are successfully developed with 82nm feature size. These novel processes drastically improved electrical characteristics such as cell capacitance, parasitic bit line capacitance and cell contact resistance, compared to a conventional process. The most pronounced effect using the LERI in COB structure is to greatly improve cell capacitance without twin bit failure. In addition, the TSC technology has an ability to remove a critical ArF lithography. By using the LERI and TSC processes in 82nm 512M DDR DRAM, the cell capacitance of 32fF/cell is achieved with Toxeq of 2.3nm and the parasitic bit line capacitance is reduced by 20%, resulted in great improvement of tRCD (1.5ns).

Analysis of Thermal Variation of DRAM Retention Time

Variation of DRAM retention time induced by thermal stress was investigated. Thermal activation energies (Ea) of sub-threshold leakage, junction leakage and GIDL (Gate Induced Drain Leakage) current of a DRAM cell were measured using the test vehicles. The values were compared with Ea of 1/tREF for the DRAM cell of which the retention time had been varied after a thermal stress. Ea of 1/tREF for the thermally degraded DRAM cell was in the range of that for GIDL current, while Ea for the normal DRAM cells with high retention time was in the range of Ea for junction leakage. It is insisted that the thermal degradation of retention time is induced by increase in GIDL current. The contributions of gate oxide/substrate interface states to the GIDL current are discussed

Interlayer design verification methodology using contour image

Memory industry has been pursuing endless shrinking technology which increases fabrication complexity. It poses problems between adjacent layers as well as within a single layer. To verify the interlayer design, we have developed the interlayer design verification methodology using contour image. Our methodology makes it possible to verify interlayer design visually by extracting the contour image from the real patterns. And we can verify interlayer design even during the fabrication process and conduct a non-destructive inspection. Also this methodology provides a statistical analysis of massive measured data. Through this methodology, we can calculate the margin of current interlayer design and suggest the requirement of design.

A novel methodology for building robust design rules by using design based metrology (DBM)

This paper addresses a methodology for building robust design rules by using design based metrology (DBM). Conventional method for building design rules has been using a simulation tool and a simple pattern spider mask. At the early stage of the device, the estimation of simulation tool is poor. And the evaluation of the simple pattern spider mask is rather subjective because it depends on the experiential judgment of an engineer. In this work, we designed a huge number of pattern situations including various 1D and 2D design structures. In order to overcome the difficulties of inspecting many types of patterns, we introduced Design Based Metrology (DBM) of Nano Geometry Research, Inc. And those mass patterns could be inspected at a fast speed with DBM. We also carried out quantitative analysis on PWQ silicon data to estimate process variability. Our methodology demonstrates high speed and accuracy for building design rules. All of test patterns were inspected within a few hours. Mass silicon data were handled with not personal decision but statistical processing. From the results, robust design rules are successfully verified and extracted. Finally we found out that our methodology is appropriate for building robust design rules.

Study on design rule verification procedure of semiconductor memory devices by using design based metrology (DBM)

At the early stage of development of semiconductor memory devices, design rule should be defined for providing design guidelines to the design engineers. Those design rules are usually expressed in terms of minimum sizes of simple patterns which describe lithography and process limitations. However the real chip designs consist of a variety of complex patterns, so minimum size design rules of simple patterns are not enough for optimizing design layout. Therefore, design rules considering various design patterns are more advisable rather than simple minimum rules. But it is not easy to setup those design rules due to the difficulties of a large number of pattern verification. In our work, we evaluate design rule verification procedure by using Design Based Metrology (DBM) to overcome the difficulties of inspecting many type of patterns. We designed a large number of test patterns including various 1D and 2D design structure. And those patterns could be inspected at a fast speed with a design based metrology. From all the measurement data, the proper design rules successfully introduced and verified. Finally we found out the suggested procedure is a suitable method for verifying design rules.

Lateral-Extended (LatEx.) active for improvement of data retention time for sub 60nm DRAM era

A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthreshold slope due to decreased cross-sectional area of top trench profile and vertical bottom trench process. In this paper, LatEx active coupled with SRCAT is proved to be suitable for sub 60 nm DRAM cell array transistor technology.