Yasuo Unekawa

A single-chip 802.11a MAC/PHY with a 32 b RISC processor

An 802.11a compliant MAC/PHY processing chip has been successfully fabricated in 0.18 /spl mu/m CMOS. Thirty million transistors are integrated on a 10.91 /spl times/ 10.91 mm/sup 2/ die in a 361-pin PFBGA. The MAC functions are fully implemented by firmware on an embedded 32 b RISC processor and hardware acceleration logic. The PHY supports a complete set of data rates up to 54 Mb/s.

A 5 Gb/s 8/spl times/8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200 MHz LVDS interface

The switch element (SE) is a 622Mb/s, 8/spl times/8 shared-buffer ATM switch LSI for backbone LAN and WAN applications. The SE has 5 Gbps bandwidth, supporting 5 QoS classes delay priority and link-by-link multicast. Up to a 32/spl times/32 switch with 20 Gbps bandwidth can be configured using multiple SEs and distributor/arbiter (DA) LSIs.

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing

Time-domain analog and digital mixed-signal processing (TD-AMS) is presented. Analog computation is more energy- and area-efficient at the cost of its limited accuracy, whereas digital computation is more versatile and derives greater benefits from technology scaling. Besides, design automation tools for digital circuits are much more sophisticated than those for analog circuits. TD-AMS exploits both advantages, and is a solution better suited to implementing a system on chip including functions for which high computational accuracy is not required, such as error correction, image processing, and machine learning. As an example, a low-density parity-check (LDPC) code decoder with the technique is implemented in 65 nm CMOS and achieves the best reported efficiencies of 10.4 pJ/bit and 6.1 Gbps/mm2.

A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing

Analog computation is potentially more efficient in certain arithmetic operations since a single wire can represent multiple bits of information, while digital systems retain advantages, for example, in logical operations. However, the use of conventional voltage-domain analog computation [1, 2] is limited due to its poor scalability, design complexity, and the overhead of interface circuits (i.e. ADC/DAC) to a surrounding digital system. Therefore, an alternate technique is required for exploiting the efficiency of analog computation. In this paper, we propose time-domain analog and digital mixed (TDMixed) signal processing, wherein time instead of voltage is utilized as the analog signal. To verify the validity of the TDMixed signal processing, we implement an (32, 8) low-density parity-check (LDPC) decoder in 65nm CMOS. The decoder achieves power and area efficiencies of 10.4pJ/b and 6.1Gb/s/mm2, respectively.

A −70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS

TransferJet™ is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer of up to 522Mbps within a few centimeters range. We have developed a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz bandwidth (BW) using 65nm CMOS technology. Baseband filtering techniques for both a transmitter (TX) and a receiver (RX) are proposed to obtain a sensitivity of -70dBm with low power consumption. The SoC achieves an energy per bit of 0.19nJ/bit and 0.43nJ/bit for the TX and the RX, respectively, We have also built the worlds smallest module prototype using the SoC, which is suitable for small mobile devices.

Shared data line technique for doubling the data transfer rate per pin of differential interfaces

A technique for almost doubling the data transfer rate per pin of the differential interfaces has been proposed. In this technique the number of the differential transmission lines between transmitter LSI and the receiver LSI are shared with adjacent buffers to increase the transfer rate per pin. Each receiver consists of two comparators and a decoder circuit translates the signal voltage at the receiver end of the transmission line into digital data. A data rate of 1.1 Gbps/pin has been achieved in the fabricated test circuit in CMOS technology.

A 65nm CMOS, 1.5-mm Bluetooth transceiver with integrated antenna filter for Co-existence with a WCDMA transmitter

This paper presents a fully integrated Bluetooth transceiver in a 65 nm CMOS, which occupies 1.5 mm2 on the chip. It even integrates an antenna filter to reject blocker from the co-existing wireless system such as WCDMA and GSM. The frequency response of the antenna filter is controlled by an onchip temperature monitor. The antenna filter achieves 30 dB rejection over the entire WCDMA band-I of 1920-1980 MHz with the temperature range from -40 to 80 °C. The transceiver achieves RX sensitivity of -89.1 dBm and TX output level of +4 dBm.

4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control

Multiphase DC-DC converters are essential to provide good efficiency over a wide range of load current, especially for todays multicore SoCs, which usually have a wide range of current profile. Active-phase-count (APC) control, as proposed in [1-3], is the key technique that offers the wide load range, and dynamically adjusts the number of phases according to load conditions. However, an APC transition induces a voltage disturbance due to current redistribution among phases. This makes the APC control only suitable for a voltage regulator with large output capacitors beyond 1000μF, or with high switching frequency beyond 10MHz [4] that hardly delivers more than 2A current with a good efficiency. To mitigate the disturbance impact, [2] has proposed adding or dropping a phase slowly, to allow the PID control to gradually redistribute the phase currents. However, the load current may change direction spontaneously before the completion of the transition, leading to deterioration in the transient response. This paper presents a fast APC scheme which performs the transition within 1 switching cycle, and only requires 66μF capacitors to limit the voltage ripple within 10mV, an 88% ripple reduction with respect to the optimal PID-only control. The proposed APC scheme utilizes digital phase current data, which is also needed to determine the optimal phase count [1-3]. However, the A/D conversions consume 3mW, which is 28% of the total power consumption. A continuous-time/discrete-time (CT/DT) hybrid current control architecture is introduced to eliminate the 3mW penalty while producing A/D converted data by time sharing of the analog circuitry in the control loop. Moreover, a fast transient response configuration is designed, offering less than 40mV fluctuation during an 8A load transition and less than 5mV fluctuation during a 2V line transition.

An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensation

A completely-digital, on-chip performance monitor circuit is newly proposed. In addition to a traditional ring-oscillator, the circuit has a special buffer-line whose output duty ratio is emphasized by the difference in performance between NMOS and PMOS transistor. Thus the performance of NMOS and PMOS transistor can be estimated independently. As the monitor is designed with area-efficient by standard-cells only, it can be used widely. To demonstrate the accuracy of performance estimation and the usability of the monitor, we have fabricated the monitor in 90nm CMOS process. The estimation errors of the drain saturation current of NMOS and PMOS transistors are 2.0% and 3.4%, respectively. We also successfully reduced the output amplitude variation of D/A converter to 50% by the calibration with the estimated results by using the monitor.

A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor

Software Defined Ratio (SDR) is indispensable technology when wireless baseband processing has to support a wide variety of wireless communication standards. This paper describes the implementation and software optimization for IEEE 802.16e (Mobile WiMAX) on ADRES, a coarse-grained dynamic reconfigurable processor. The paper also explains switching between 802.11a (WLAN) and 802.16e at runtime. The switching time is 2.6 milliseconds which is shorter than 5.0 milliseconds, 1 frame time period of 802.16e specification.