Dale Becker

Signal propagation over perforated reference planes

Voids on reference planes are commonly seen in organic chip packages and printed circuit boards. In this paper, the effects of these voids on the signal integrity of a high-density data bus will be studied. A generic FCPBGA chip package is used to illustrate the signal integrity concerns and perform sensitivity analysis on the key mechanisms including void size, adjacent plane interactions, and adjacent signal line interactions. The results show that proper design can mitigate the signal integrity impact of reference plane voids.

Performance effects of switching noise on CMOS microprocessors

The simultaneous switching noise of off-chip drivers and internal circuits affect the performance of the CMOS chips. These effects are quantified using voltage waveforms obtained from simulations on a high-frequency package model.

A case study of high-speed serial interface simulation with IBIS-AMI models

High-end, high-performance computers use high-speed serial interfaces to pass data and control signals between the electronic components in the systems. These interfaces include proprietary interfaces unique to a class of systems and some interfaces, such as PCIe & SAS, which have publicly available standards and specifications that enable communication between electronic components from different manufactures. The IBIS-AMI model has been developed to facilitate circuit simulation of high-speed serial interfaces and is particularly useful in simulating communication between transmitters and receivers procured from different manufactures. The simulations are performed to ensure that the interface specifications are met, including the eye characteristics, and that the bit error rate (BER) is less than a specified maximum. There are many variables and long bit strings needed to predict a BER of sufficiently low amplitude. Therefore, an efficient and accurate estimation of BER requires significantly long simulations times. In this paper, we use the example of a 6 gigabit per second (Gb/s) SAS interface to illustrate our proposed simulation method of combining an empirical and analytical approach to estimate the effects of inter-symbol interference (ISI) and channel jitter using an IBIS-AMI models.

Massively parallel full-wave modeling of advanced packaging structures on BlueGene supercomputer

A parallel, distributed memory version of a full wave method of moments (MoM) solution combined with the reduced coupling approximation technique is presented on the largest parallel-server. Modeling results for product-level simulation of a single-chip module are correlated with time- domain measurements for validation of the technique. Scaling for this and other representative examples are shown for up to 16,384 compute nodes on IBMs BlueGene supercomputer, the largest parallel-platform ever reported for MoM based solutions.

Compact physical models for chip and package power and ground distribution networks for gigascale integration (GSI)

For the first time, compact physical models are derived in this work that enable quick package- and chip-scale calculations of the power supply noise and incorporate the distributed natures of on-chip power/ground grids and package-level power/ground planes. Designers can use these models to perform chip/package co-design for power distribution networks and tradeoff multiple design considerations such as metal resource allocation on chip and in package, decoupling capacitor insertion and I/O allocation. Such studies can be performed during early stages of design, even when detailed physical design information is not available. The models are used to model a ceramic package designed by IBM, and it is found that there is less than 10% difference between the model predictions and the commercial tool SPEED 2000 when predicting the peak noise value and time of occurrence. The models can have 10times speed-up compared to SPEED 2000.

Vref optimization in DDR4 RDIMMs for improved timing margins

JEDEC DDR4 SDRAM adopted the internal Data (DQ) reference voltage (VREFDQ) generation scheme as opposed to DDR3 SDRAM where VREF was generated by an external device that produced fixed (constant) voltage irrespective of the loading on the device, power supply variations, temperature changes, and the passage of time. With the introduction of Per DRAM Addressability (PDA) in DDR4 memory and the internal VREF combined, discussed in this paper is a novel approach to determine the best VREF settings for a given topology. We will use memory controller built-in-self-test (MCBIST) to get a stressed pattern in place of simple Multi Purpose Register (MPR) data pattern and will be exercised as part of post DRAM training. Data pattern complexity, total training time and accuracy of training are investigated and optimized. Initial training of the DRAM is done with the initial VREF calculated based on driver strength and On Die Termination (ODT) condition. Complexities of different VREF settings are applied on multiple ranks in the same DIMM using the PDA to maximize timing margin and power efficiency. Per-DRAM VREF training has been also performed using PDA to study tradeoff between timing margin and total training time. Our results show significant benefits with respect to PDA vs rank basis Vref training.

Modeling and analysis of package PDN for computing system based on cavity model

Recent computing systems consume more than several hundred watts of power and a robust PDN design is critical to minimize power/ground (P/G) voltage fluctuation and get stable performance. In most cases, the IC package (PKG) PDN determines mid-frequency P/G noise characteristics. The PDN of our target IC package consists of more than ten thousands staggered microvias and tens of layers, representing a significant modeling challenge. Commercial tools can estimate the PKG PDN impedance via full-wave simulations, but it has several limitations at pre-layout stage. Whole simulation should be run for every small geometry changes and it takes much time. It can give circuit model seen at port, but does not provide physics-based circuit models corresponding to whole current path. In this paper we apply the cavity model, which has been previously largely used for PCB modeling, to a complex organic package structure. We here describe the assumptions used to get an equivalent circuit model for this type of geometry and the comparison of its loop inductances with commercial tools. The cavity model gives about 10 % error compared to commercial tool and the reason of error is analyzed. In addition, a study of the PKG decoupling capacitors location is performed with the goal of a minimal loop inductance. In the final paragraph, several unique features of the PKG PDN compared to PCB PDN modeling are described.

Package and Printed Circuit Board Design of a 19.2 Gb/s Data Link for High-Performance Computing

A 19.2 Gb/s per lane link with IBMs latest POWER8 processor module has been analyzed. This paper presents the overview of the high-speed link design from the signal integrity point of view. Design approaches in package and printed circuit board (PCB) to support the target data-rate have been discussed. The end-to-end communication bus is modeled from extracted post-route design with a 3-D full-wave extractor and has been simulated with IO properties at system level. Bath-tub curves are generated from data gathered in functioning systems running this 19.2 Gb/s link to confirm the operation of the link meets the required bit-error-rate criteria as the modeling and simulation predicted.

Realization of ultra-low power I/O

This paper summarizes the exploratory work conducted at IBM which seeks to reduce electrical I/O power consumption to facilitate both power distribution and device cooling for future exascale computing systems. The development of novel low-loss dielectric materials was coupled with design for performance to achieve low channel loss by minimizing reflections and energy dissipation due to non-ideal current return paths. A printed circuit board was fabricated and tested, with results confirming a 20% reduction of channel loss at 10GHz when compared to currently leading commercial materials. This 3dB improvement in loss for a 15dB channel, can offer a 50% I/O power reduction when used with power scalable driving/receiving circuits.

Wire and via modeling and simulation solutions for a tri-grid mesh plane ceramic packaging

To accurately evaluate interconnect net electrical properties of the tri-grid structure we need to model the wires and vias in this structure. Due to the high application frequencies and the non-TEM nature of the propagating mode in this structure, the use of full-wave electromagnetic tools is necessary. In this paper we describe the principles and results of three different modeling and simulation solutions. The modeling and simulation solutions are based on full-wave electromagnetic simulations on short physical structure sections. The solutions can be applied to the transient circuit simulation on longer interconnect nets for evaluating system reflection, transmission, near end noise, and far end noise. The comparison shows the per-unit-length RLGC is the most efficient model and simulation method for this application