Taylor R. Efland

A Rugged LDMOS for LBC5 Technology

This paper presents a new method of enhancing the SOA of n-channel Ldmos transistors. Attention is focused on those applications where “Electrical SOA” is important and where the power pulse time is typically a few µs or less. Typical applications include gate drives, H-bridge commutation, and self-protection against ESD pulses.

SCR-LDMOS. A novel LDMOS device with ESD robustness

A novel lateral power device structure with a very high degree of ESD (electrostatic discharge) robustness is presented. This device called the SCR-LDMOS is a modification of the lateral LDMOSFET with good on state and blocking characteristics.

Lateral thinking about power devices (LDMOS)

BiCMOS Power technology LDMOS are reviewed with respect to category and structure definition and briefly as to how the structures relate to figure of merit performance. Stepped gate oxide devices are introduced making use of popular dual gate technologies and exhibit improved R/sub sp/ vs. BV performance of up to 30% at low V/sub gs/ without sacrifice of BV. Production use of thick copper plated bussing up to 25 /spl mu/m thick with R/sub sh/=0.8 m/spl Omega//sq is revealed for power, enabling up to 40% efficiency improvement on LDMOS power transistors.

Avalanche-induced thermal instability in Ldmos transistors

Safe operating area limits for large Ldmos are shown to be due to a thermal instability mechanism initiated by avalanche generated carriers which turn-on the parasitic bipolar transistor. An analytic model is described and is shown to agree well with experimental data.

16-60 V rated LDMOS show advanced performance in a 0.72 /spl mu/m evolution BiCMOS power technology

In this work, performance advances are featured for new and improved multi voltage rated (16 V to 60 V) LDMOS. Performance improvements were achieved by leveraging off of (1) an optimized off-set, photo aligned, coimplanted double-diffused well (DWL), (2) two n-type dopings in the drift region, and (3) shrink from 1.0 /spl mu/m to 0.72 /spl mu/m. The R/sub sp/ vs. BV/sub dss/ trend for these devices is the best reported to date for conventional lateral technology: @V/sub gs/=12.75 V (3 MV/cm) R/sub sp/=0.95 m/spl Omega/ cm/sup 2/, BV=69.3 V; R/sub sp/=0.68 m/spl Omega/ cm/sup 2/, BV=50.0 V; R/sub sp/=0.45 m/spl Omega/ cm/sup 2/, BV=33.0 V; R/sub sp/=0.36 m/spl Omega/ cm/sup 2/, BV=19.0 V; for 60, 40, 25, and 16 V rated conventional LDMOS devices.

Optimized complementary 40 V power LDMOS-FETs use existing fabrication steps in submicron CMOS technology

This paper discusses development of state-of-the-art complementary isolated lateral 40 V rated power MOSFETs. The goals of this project were to provide BV specific devices for use with an existing merged VLSI technology. Devices meeting this goal were fabricated in a production manufacturing environment with no extra cost added to the process. The p-channel FET has a BV=60 V, and R/sub s/p=2.71 m/spl Omega/ cm/sup 2/ @V/sub gs/=15 V, and for the n-channel FET, BV=47 V and R/sub sp/=0.67 m/spl Omega/cm/sup 2/ @V/sub gs/=15 V. These devices are seen to be very competitive solutions with advanced integral on-chip intelligence.<<ETX>>

Analysis of high current breakdown and UIS behavior of resurf LDMOS (RLDMOS) devices

This work analyzes unclamped inductive switching (UIS) behavior of two types of 40 V resurf (reduced surface field) lateral diffused MOSFETs (RLDMOSFETs). It is shown that the addition of a deep buffer implant region on the drain side of the device increases the snap-back current limit as well as UIS robustness. It is also shown, using 2D simulation, that the failure current limit under UIS conditions is not the same as the current at which the parasitic BJT turns on.

A performance comparison between new reduced surface drain "RSD" LDMOS and RESURF and conventional planar power devices rated at 20 V

This work presents a new reduced-surface-drain (RSD) type of LDMOS in comparison with very thin RESURF (VTR) and conventional (CONV) devices for 20 V BiCMOS market applications. Competitive performance results obtained for the RSD, VTR and CONV devices are respectively R/sub sp/=0.39 m/spl Omega//spl middot/cm/sup 2/ BV=24.4 V; R/sub sp/=0.30 mn/spl Omega//spl middot/cm/sup 2/, BV=25 V; R/sub sp/=0.59 m/spl Omega//spl middot/cm/sup 2/, BV=18-20 V. All R/sub sp/, measurements are with 3 MV/cm gate stress(V/sub gs/=12.75 V, Tox=425 /spl Aring/).

Current status and future trends in silicon power devices

Overall, power semiconductors are very much alive and well. Silicon dominates the field with a high quality R&D effort and manufacturing workforce supported by an extensive infrastructure. Much of this success can be linked to the numerous desirable material properties of silicon. These include the presence of a native oxide with low interface state density, reasonable values for hole and electron mobilities, a high critical electric field, high carrier lifetimes, and finally, good thermal conductivity. Other materials, for example SiC and GaN, are superior to silicon in some of these properties. This has led to product applications where a particular need dominates the application. For example, SiC has a higher critical field vs. silicon. This permits the design of 600V SiC Schottky diodes that are superior to their silicon counter parts, whether it is a p-n junction or a Schottky diode. Because such developments enhance the overall industry, we should encourage them. Nevertheless, it seems that power semiconductors will continue to be dominated by silicon for the next few decades.

The Earth is mobile-power

Mobile power or portable power is typically defined as battery cell operated. An important requirement is the operation from various portable energy sources. This requirement is driven on the low end by operation from a single cell 1.2V Nickel Metal Hydride with a final discharge voltage of 0.8V. The requirement on the high end is from multiple cell LiIon batteries with up to four cells in series each having a nominal voltage of 3.7V. Transient switching, adaptor interface regulation, and fault protection may drive the required system input levels even higher. With the addition of display technology the voltage rating of devices reaches upward to 35V. Typically mobile power IC current ratings can be as low as 50 mA for single cell NiMH applications and upward to 5-7A on the 3-4 cell LiIon applications. Even though the actual power level appears to be low, it requires all of the same safe operating limits and attention to power but on low voltage scale. Mobile power is one of the most diverse application areas for power semiconductor ICs. When you think about mobile devices, they are simple in operation and small in appearance but contain a very complex and functional system internally. Examples of such products are notebook PCs, PDAs, cell phones, pagers, MP3 players, minidisk, CD, DVD, GPS, portable signal transmission and reception (fish finder), robots, games, and a host of others, Generally, mobile product systems may consist of: processors and/or DSPs; a user interface - keys, display, and audio; communication and hardware interface compatible capability; wireless capability; battery management; charging and selection from external power sources; and standard switching, regulation, control, and conversion of power. The range of power applications for these mobile products includes: battery management such as various sophistication of capacity gauging for battery functionality in and outside of battery packs, battery or charger selection and interface, battery protection, and multiple battery operation. There is also power distribution involving large scale highly integrated SOC chips, a good example is cell phone power management; system power on board which includes integrated or singular functions such as, smart power, conversion, controllers, and switches. Another area is display bias and lighting, and audio, and RF power for wireless signal transmission, and indirectly specific application power such as PCMCIA, USB, storage products, and other macro systems with power needs within the mobile systems. The trends in mobile systems are to increase functionality for the user, increase battery life/power efficiency, increase interface quality and compatibility, and decrease weight and size of the system. For example, when thinking about a PDA, ideally if it was as thin as the display, and the size of the display, then the smallest form-factor would be obtained. For hand held portable, thin is in. This drives the trend to integrate chip scale functionality at a higher level. This in turn drives a shrinking and diverse process technology lithography roadmap needing many special functions, a thinner and smaller form-factor package roadmap with efficient power handling capability, and of course, all of this complexity at a low-cost. This implies that the range and span of technology to harness these applications is very broad. Indeed optimization tradeoffs to yield competitive power device performance combined with the need for SOC level integration, precision analog functionality, robust ESD, and efficient memory, presents a very complex and challenging technology roadmap.