Chin-Yu Tsai

Lateral thinking about power devices (LDMOS)

BiCMOS Power technology LDMOS are reviewed with respect to category and structure definition and briefly as to how the structures relate to figure of merit performance. Stepped gate oxide devices are introduced making use of popular dual gate technologies and exhibit improved R/sub sp/ vs. BV performance of up to 30% at low V/sub gs/ without sacrifice of BV. Production use of thick copper plated bussing up to 25 /spl mu/m thick with R/sub sh/=0.8 m/spl Omega//sq is revealed for power, enabling up to 40% efficiency improvement on LDMOS power transistors.

Avalanche-induced thermal instability in Ldmos transistors

Safe operating area limits for large Ldmos are shown to be due to a thermal instability mechanism initiated by avalanche generated carriers which turn-on the parasitic bipolar transistor. An analytic model is described and is shown to agree well with experimental data.

16-60 V rated LDMOS show advanced performance in a 0.72 /spl mu/m evolution BiCMOS power technology

In this work, performance advances are featured for new and improved multi voltage rated (16 V to 60 V) LDMOS. Performance improvements were achieved by leveraging off of (1) an optimized off-set, photo aligned, coimplanted double-diffused well (DWL), (2) two n-type dopings in the drift region, and (3) shrink from 1.0 /spl mu/m to 0.72 /spl mu/m. The R/sub sp/ vs. BV/sub dss/ trend for these devices is the best reported to date for conventional lateral technology: @V/sub gs/=12.75 V (3 MV/cm) R/sub sp/=0.95 m/spl Omega/ cm/sup 2/, BV=69.3 V; R/sub sp/=0.68 m/spl Omega/ cm/sup 2/, BV=50.0 V; R/sub sp/=0.45 m/spl Omega/ cm/sup 2/, BV=33.0 V; R/sub sp/=0.36 m/spl Omega/ cm/sup 2/, BV=19.0 V; for 60, 40, 25, and 16 V rated conventional LDMOS devices.

Analysis of high current breakdown and UIS behavior of resurf LDMOS (RLDMOS) devices

This work analyzes unclamped inductive switching (UIS) behavior of two types of 40 V resurf (reduced surface field) lateral diffused MOSFETs (RLDMOSFETs). It is shown that the addition of a deep buffer implant region on the drain side of the device increases the snap-back current limit as well as UIS robustness. It is also shown, using 2D simulation, that the failure current limit under UIS conditions is not the same as the current at which the parasitic BJT turns on.

A performance comparison between new reduced surface drain "RSD" LDMOS and RESURF and conventional planar power devices rated at 20 V

This work presents a new reduced-surface-drain (RSD) type of LDMOS in comparison with very thin RESURF (VTR) and conventional (CONV) devices for 20 V BiCMOS market applications. Competitive performance results obtained for the RSD, VTR and CONV devices are respectively R/sub sp/=0.39 m/spl Omega//spl middot/cm/sup 2/ BV=24.4 V; R/sub sp/=0.30 mn/spl Omega//spl middot/cm/sup 2/, BV=25 V; R/sub sp/=0.59 m/spl Omega//spl middot/cm/sup 2/, BV=18-20 V. All R/sub sp/, measurements are with 3 MV/cm gate stress(V/sub gs/=12.75 V, Tox=425 /spl Aring/).

Optimized 25 V, 0.34 m/spl Omega//spl middot/cm/sup 2/ very-thin-RESURF (VTR), drain extended IGFETs in a compressed BiCMOS process

The competitive PC peripheral application market drives the goal to develop a compressed, low-cost BiCMOS power technology with state-of-the-art specific-on-resistance (R/sub sp/) at the 20 V node. The 20 V rated lateral power device is difficult to optimize because modern VLSI processes tend to physically limit surface BV to about 13-19 V in planar devices. Here the structure performance is advanced by optimizing a Very-Thin-RESURF (VTR) region (VTR Xj=0.3 /spl mu/m). This work presents a planar VTR drain extended IGFET with best case BV=25 V and R/sub sp/=0.34 m/spl Omega//spl middot/cm/sup 2/@V/sub gs/=10 V using a compressed BiCMOS VLSI, 1 /spl mu/m technology. Structure variation and thermal performance are characterized.

Robust 80 V LDMOS and 100 V DECMOS in a streamlined SOI technology for analog power applications

A new 80 V SOI process is described with best in class LDMOS performance. The use of standard SOI material, deep trench isolation, a simplified process flow, and a well defined component set make this technology well suited for telecom, industrial, and automotive applications.

A 3V to 6V in, 6A out synchronous buck PWM integrated FET switcher design uses state-of-art power IC technology

A 3V to 6V input, 6A output synchronous buck PWM switcher with integrated FETs; TI code name SWIFT/spl trade/ has been fabricated using a combination of past reported power IC technology. In this IC we extended a production 0.72/spl mu/m technology with enhanced features and then combined mixed circuit design with integrated thin-gate oxide, planar, very-thin-resurf VTR LDMOS FETs. The Power IC uses plated CuNiPd top metal for low resistance busing and bonding over active area and is packaged in a thin line 28 pin TSSOP package having a POWERPAD/spl trade/. The technology combination yields a state-of-art performance power IC. The device is capable of 95% efficiency and is excellent for point-of-load applications such as DSP solutions as well as high density distributed power systems. The key to high efficiency in this product is dual low Ron=30 m/spl Omega/ fets, low gate charge losses, and low reverse recovery losses during power FET switching.

Split gate MOSFET in BiCMOS power technology for logic level gate voltage application

Utilizing dual gate BiCMOS power technology (BPT), split gate oxide LDMOS and CMOS structures have been fabricated. These structures take advantage of low on-state channel resistance under the thin gate oxide at the source side and high breakdown voltage under the thick gate oxide at the drain side. Device simulation shows performance improvement in both R/sub ds-on/ at low V/sub gs/ and a reduction in field crowding in the reverse blocking state. Experimental characterization proves more efficient transistors can be integrated utilizing dual gate oxide at logic level gate drive while maintaining high breakdown voltage compared with single gate oxide devices.