Danfeng Chen

A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers

This paper presents the design of a sideband-suppressed synthesizer for dual-carrier MB-OFDM transceivers covering 11 frequency bands from 6.2GHz to 9.4GHz and 3 frequency bands from 4.2GHz to 4.8GHz, each with a bandwidth of 264MHz. Careful band plan is made to minimize the complexity. The synthesizer generates 14 carrier frequencies from a single frequency source. Improvements are made to the circuits to further suppress the sidebands. The synthesizer chip is designed with TSMCs 0.13-µm RF CMOS technology. The circuit draws a current of 42mA from a 1.2V supply. It achieves a sideband rejection of 45dBc and a phase noise of −105dBc/Hz@lMHz.

An improved Phase/Frequency Detector and a glitch-suppression charge pump design for PLL applications

This paper presents an improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications. The output signals of the proposed PFD have perfect symmetry with the additional four latches. Two small PMOS transistors and two inverters are added to work as level recovery to avoid the uncertain state of PFD when the circuit powers on. The proposed CP circuit employs two rail-to-rail OP amplifiers to minimize the mismatch between the charging and the discharging current, which minimizes the steady-state phase error in a PLL and reduces the reference spurs. Moreover, a simple but effective technique is proposed to suppress the glitches of the output current, which also decreases the level of reference spurs in a PLL and at the same time increases the dynamic range of the CP. A PLL adopting the proposed PFD and CP is fabricated in TSMC 0.13um 1.2V CMOS process, and test results indicate that the PLL can achieve −56dBc reference spur level.

A 8.5 GHz phase locked loop with split-load divider

This paper presents a 8448MHz phase-locked loop (PLL) with a proposed divider implemented in 0.13 µm CMOS technology. Compared with conventional current mode logic (CML) divider, the proposed split-load divider presents wider operating frequency range and lower power dissipation. The ratio of the locking range over the center frequency is up to 70% depending on the operating frequency. It consumes around 5mW power with 1.2V supply. The 8448 MHz PLL achieves phase noise of −92 dBc/Hz at frequency offsets of 100 kHz and has a reference spur of -56 dB with the second order passive low pass filter. The whole circuit (without test buffer) consumes only 13mA for a 1.2V power supply with die area of 0.9×1.3mm2.

Electromagnetic field distribution calculation in solenoidal inductively coupled plasma using finite difference method

The electromagnetic field (both E and B fields) is calculated for a solenoidal inductively coupled plasma (ICP) discharge. The model is based on two-dimensional cylindrical coordinates, and the finite difference method is used for solving Maxwell equations in both the radial and axial directions. Through one-turn coil measurements, assuming that the electrical conductivity has a constant value in each cross section of the discharge tube, the calculated E and B fields rise sharply near the tube wall. The nonuniform radial distributions imply that the skin effect plays a significant role in the energy balance of the stable ICP. Damped distributions in the axial direction show that the magnetic flux gradually dissipates into the surrounding space. A finite difference calculation allows prediction of the electrical conductivity and plasma permeability, and the induction coil voltage and plasma current can be calculated, which are verified for correctness.