Haipeng Fu

Design and Analysis of Wide Frequency-Tuning-Range CMOS 60 GHz VCO by Switching Inductor Loaded Transformer

To provide wide frequency tuning range (FTR) with compact implementation area, a new inductive tuning method is introduced in this paper for CMOS 60 GHz voltage controlled oscillator (VCO). The inductive tuning is based on a switching inductor-loaded transformer by configuring different current return-paths in the secondary coil of the transformer. Different from previous inductive tuning methods, the proposed VCO topology can achieve wide FTR for multiple sub-bands at 60 GHz within compact area by only one transformer. Two 60 GHz VCOs are demonstrated in 65 nm CMOS with design targets for the maximum FTR and the balanced phase noise in each sub-band, respectively. As measured by experiments, the first VCO (asymmetric) achieves a wide FTR of 25.8% from 51.9 to 67.3 GHz with phase noise variation of ±8.2 dB ( -90.2 to -106.7 dBc/Hz at 10 MHz offset) in all sub-bands; and the second VCO (symmetric) realizes a low phase noise variation of ±2.5 dB ( -105.9 to -110.8 dBc/Hz at 10 MHz offset) in all sub-bands with a FTR of 14.2% from 57.0 GHz to 65.5 GHz.

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter

A 2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise is introduced in this paper. A new phase detection mechanism using aperture-phase detector (APD) and phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error between reference and VCO, and then controls the current amplitude of the following charge pump (CP). The charging and discharging currents in the proposed CP have equal pulse width and equal small amplitude in locked state, which reduces the reference spur and power consumption of the CP effectively. Moreover, compared to the conventional CP with the same bias current in locked state, the proposed CP can contribute a much lower noise to the PLL output. In addition, a method of tunable loop gain with theoretical analysis is introduced to reduce the PLL output jitter. The proposed PLL is fabricated in a standard 0.13-μm CMOS process. It consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm × 0.86 mm. The reference spur of the proposed PLL is measured to be -80 dBc/-74 dBc and an in-band phase noise of -103 dBc/Hz at 100 kHz offset is achieved.

A sideband-suppressed low-power synthesizer for 14-band dual-carrier MB-OFDM UWB transceivers

This paper presents the design of a sideband-suppressed synthesizer for dual-carrier MB-OFDM transceivers covering 11 frequency bands from 6.2GHz to 9.4GHz and 3 frequency bands from 4.2GHz to 4.8GHz, each with a bandwidth of 264MHz. Careful band plan is made to minimize the complexity. The synthesizer generates 14 carrier frequencies from a single frequency source. Improvements are made to the circuits to further suppress the sidebands. The synthesizer chip is designed with TSMCs 0.13-µm RF CMOS technology. The circuit draws a current of 42mA from a 1.2V supply. It achieves a sideband rejection of 45dBc and a phase noise of −105dBc/Hz@lMHz.

A 2.1-GHz PLL with −80dBc/−74dBc reference spur based on aperture-phase detector and phase-to-analog converter

This paper presents a 2.1-GHz PLL with low power consumption, low in-band phase noise and low reference spur. A new aperture-phase detector (APD) compares the phases between reference and VCO output in a time window, which eliminates the power and noise contributions from the divider. At the end of phase detection, a phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error and then controls the current amplitude of the following charge pump (CP) circuit. When transferred to PLL output, CP noise is not multiplied by N2 compared with a conventional PLL, which leads to the PLL with lower in-band phase noise. In the proposed CP, the charging and discharging currents have equal pulse width and equal amplitude close to zero when PLL is locked, resulting in a low reference spur and super-low power consumption of CP. The proposed PLL is implemented in TSMC 0.13μm CMOS process, which consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm × 0.86 mm excluding PAD. Measurement results indicate that the PLL achieves a reference spur level of −80dBc/−74dBc, and an in-band phase noise of −103 dBc/Hz at 100 kHz offset.

An improved Phase/Frequency Detector and a glitch-suppression charge pump design for PLL applications

This paper presents an improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications. The output signals of the proposed PFD have perfect symmetry with the additional four latches. Two small PMOS transistors and two inverters are added to work as level recovery to avoid the uncertain state of PFD when the circuit powers on. The proposed CP circuit employs two rail-to-rail OP amplifiers to minimize the mismatch between the charging and the discharging current, which minimizes the steady-state phase error in a PLL and reduces the reference spurs. Moreover, a simple but effective technique is proposed to suppress the glitches of the output current, which also decreases the level of reference spurs in a PLL and at the same time increases the dynamic range of the CP. A PLL adopting the proposed PFD and CP is fabricated in TSMC 0.13um 1.2V CMOS process, and test results indicate that the PLL can achieve −56dBc reference spur level.

A 60.8–67GHz and 6.3mW injection-locked frequency divider with switching-inductor loaded transformer in 65nm CMOS

A CMOS 60GHz injection-locked frequency divider (ILFD) is demonstrated in this paper by introducing a wide-frequency-range switching-inductor loaded transformer. With different switching conditions, multi-band operation can be realized to improve the locking range with low power consumption and compact area. The 60GHz ILFD together with the entire divider chain is implemented in 65nm CMOS process with measured frequency range from 60.8 to 67GHz covered by two switching bands that can be utilized in 60GHz PLL design.

A harmonic-suppressed regenerative divide-by-5 frequency divider for UWB applications

A harmonic-suppressed regenerative divide-by-5 frequency divider is proposed. Incorporating the proposed quadrature-input regenerative divide-by-2 divider (QIRD), the divide-by-5 divider suppresses the output harmonic effectively. The divide-by-5 divider improves the quadrarture phase accuracy at the output. Compared with conventional dividers, the divider achieves an output I/Q phase sequence that is tracked with the input I/Q phase sequence. The design is fabricated in TSMC 0.13-um CMOS and operated at 1.2 V. While locked at 8.6 GHz, the divide-by-5 divider achieves a minimum unwanted sideband rejection of −38 dBc.

A −78dBm sensitivity super-regenerative receiver at 96 GHz with quench-controlled metamaterial oscillator in 65nm CMOS

One high-sensitivity CMOS superregenerative receiver is demonstrated for 96GHz mm-wave imaging based on high-Q metamaterial oscillator. Compared to traditional LC-tank based oscillator, the metamaterial oscillator is developed by folded-differential transmission-line loaded complimentary split-ring resonator (FDTLCSRR). With formed sharp stop-band, standing-wave is established with high EM-energy storage at mm-wave region for high-Q oscillatory amplification. As such, one high-sensitivity 96 GHz super-regenerative receiver is realized in 65nm CMOS with measurement results of: -78 dBm sensitivity, 0.67 fW/Hz0.5 NEP, 8.5 dB NF, 2.8mW power consumption and 0.014 mm2 core area.

Low phase noise injection-locked doubler-based quadrature CMOS VCO

This paper presents a low phase noise injection-locked doubler-based quadrature voltage controlled oscillator (ILD-QVCO). Instead of using conventional coupling scheme, an injection-locked doubler is introduced in the proposed ILD-QVCO to generate quadarature signals. In this architecture, phase noise is determined by the coupled VCOs, and the phase accuracy is determined by VCO oscillating at twice of the desired frequency. Thus, the trade-off between the two parameters in traditional QVCO does not exist in the ILD-QVCO. Besides, the novel QVCO proves to have a better phase noise than conventional QVCO. The proposed ILD-QVCO is designed and simulated in TSMC 130nm CMOS 1P8M process. Simulation results show that the ILD-QVCO has a phase noise of −120.4 dBc/Hz at an offset frequency of 1MHz from a 6.1GHz carrier, and draws a 7.15-mA current from a 1.2-V supply voltage. A 186.7-dB figure of merit (FOM) is achieved.

A low-voltage differential injection locked divider with forward body bias

An low voltage and wide locking range injection-locked frequency divider using a 0.13-µm CMOS is presented. The wide locking range and low-voltage operation are achieved by using forward body bias technique. A differential injection scheme is proposed to fit to the integrated differential on-chip oscillator and improve injection efficiency. When operating at a supply voltage of 0.6 V, a maximum locking range of 10.31 GHz, from the incident frequency 40.49 to 50.8 GHz, is achieved at the incident power of 0 dBm. The frequency divider consumes a static current of 6 mA.