Deyun Cai

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter

A 2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise is introduced in this paper. A new phase detection mechanism using aperture-phase detector (APD) and phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error between reference and VCO, and then controls the current amplitude of the following charge pump (CP). The charging and discharging currents in the proposed CP have equal pulse width and equal small amplitude in locked state, which reduces the reference spur and power consumption of the CP effectively. Moreover, compared to the conventional CP with the same bias current in locked state, the proposed CP can contribute a much lower noise to the PLL output. In addition, a method of tunable loop gain with theoretical analysis is introduced to reduce the PLL output jitter. The proposed PLL is fabricated in a standard 0.13-μm CMOS process. It consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm × 0.86 mm. The reference spur of the proposed PLL is measured to be -80 dBc/-74 dBc and an in-band phase noise of -103 dBc/Hz at 100 kHz offset is achieved.

Design of Ultra-Low-Power 60-GHz Direct-Conversion Receivers in 65-nm CMOS

This paper has explored an ultra-low-power design of two 60-GHz direct-conversion receivers in a 65-nm CMOS process for single-channel and multi-channel applications under the IEEE 802.15.3c standard, respectively. One subthreshold biasing 0.4-V transconductance mixer is designed with a compact quadrature hybrid coupler (160 μm × 210 μm with measured 3-dB intrinsic loss) in receivers to achieve low power (8 mW for single channel and 12.4 mW for multi-channel) and high gain (55 dB for single channel and 62-dB for multi-channel). One three-stage low-noise amplifier employs high- Q passive matchings. A double-layer-stacked inductor is utilized for matching in the single-channel receiver and a high-impedance transmission line is utilized for matching in the multi-channel receiver, respectively. In addition, one new modified Cherry-Hooper amplifier is applied for the variable-gain amplifier design to achieve high gain-bandwidth product and high power efficiency. The single-channel receiver is implemented with 0.34- mm2 chip area. It is measured with a power consumption of 8 mW, a minimum single-sideband noise figure (NF) of 4.9 dB, a 3-dB bandwidth of 3.5 GHz, and a maximum conversion gain of 55 dB. The multi-channel receiver is implemented with 0.56- mm2 chip area. It is measured with a power consumption of 12.4 mW, a 3-dB bandwidth of 8 GHz (59.5 ~ 67.5 GHz), and a maximum conversion gain of 62 dB. The measurement results show that the two demonstrated 60-GHz direct-conversion receivers can achieve high gain and low NF with ultra-low power in 65-nm CMOS.

A 96-GHz Oscillator by High-

A 96-GHz CMOS oscillator is demonstrated in this brief with the use of a high-Q metamaterial resonator. The proposed metamaterial resonator is constructed by a differential transmission line (T-line) loaded with complementary split-ring resonator engraved on the T-line. A negative real part of permittivity, i.e., , is observed near the resonance frequency, which introduces a sharp stopband and, thus, leads to a high-Q resonance. This brief is the first in literature to explore CMOS on-chip metamaterial resonator for oscillator design at the millimeter-wave frequency region. Compared with the existing oscillators with a LC-tank-based resonator at around 100 GHz, the proposed 96-GHz oscillator with high- metamaterial resonator shows much lower phase noise of 111.5 dBc/Hz at 10-MHz offset and figure-of-merit of 182.4 dBc/Hz.

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An ultra low power direct-conversion receiver is demonstrated for V-band 60GHz applications in 65nm CMOS process. The power consumption is significantly reduced by the design of low-power low noise amplifier (LNA), transconductance mixer and variable gain amplifier (VGA). A compact quadrature-hybrid coupler is developed for transconductance mixer for the reduction of both power and area. The proposed receiver (0.34mm2 chip area) is measured with 8mW power, the minimum single-side-band (SSB) noise figure (NF) of 4.9dB, and the maximum power conversion gain of 55dB.

Differential Transmission Line loaded with Complementary Split-Ring Resonator in 65-nm CMOS

This paper presents a 2.1-GHz PLL with low power consumption, low in-band phase noise and low reference spur. A new aperture-phase detector (APD) compares the phases between reference and VCO output in a time window, which eliminates the power and noise contributions from the divider. At the end of phase detection, a phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error and then controls the current amplitude of the following charge pump (CP) circuit. When transferred to PLL output, CP noise is not multiplied by N2 compared with a conventional PLL, which leads to the PLL with lower in-band phase noise. In the proposed CP, the charging and discharging currents have equal pulse width and equal amplitude close to zero when PLL is locked, resulting in a low reference spur and super-low power consumption of CP. The proposed PLL is implemented in TSMC 0.13μm CMOS process, which consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm × 0.86 mm excluding PAD. Measurement results indicate that the PLL achieves a reference spur level of −80dBc/−74dBc, and an in-band phase noise of −103 dBc/Hz at 100 kHz offset.

An 8mW ultra low power 60GHz direct-conversion receiver with 55dB gain and 4.9dB noise figure in 65nm CMOS

This paper presents an improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications. The output signals of the proposed PFD have perfect symmetry with the additional four latches. Two small PMOS transistors and two inverters are added to work as level recovery to avoid the uncertain state of PFD when the circuit powers on. The proposed CP circuit employs two rail-to-rail OP amplifiers to minimize the mismatch between the charging and the discharging current, which minimizes the steady-state phase error in a PLL and reduces the reference spurs. Moreover, a simple but effective technique is proposed to suppress the glitches of the output current, which also decreases the level of reference spurs in a PLL and at the same time increases the dynamic range of the CP. A PLL adopting the proposed PFD and CP is fabricated in TSMC 0.13um 1.2V CMOS process, and test results indicate that the PLL can achieve −56dBc reference spur level.

A 2.1-GHz PLL with −80dBc/−74dBc reference spur based on aperture-phase detector and phase-to-analog converter

A harmonic-suppressed regenerative divide-by-5 frequency divider is proposed. Incorporating the proposed quadrature-input regenerative divide-by-2 divider (QIRD), the divide-by-5 divider suppresses the output harmonic effectively. The divide-by-5 divider improves the quadrarture phase accuracy at the output. Compared with conventional dividers, the divider achieves an output I/Q phase sequence that is tracked with the input I/Q phase sequence. The design is fabricated in TSMC 0.13-um CMOS and operated at 1.2 V. While locked at 8.6 GHz, the divide-by-5 divider achieves a minimum unwanted sideband rejection of −38 dBc.

An improved Phase/Frequency Detector and a glitch-suppression charge pump design for PLL applications

This paper presents a 8448MHz phase-locked loop (PLL) with a proposed divider implemented in 0.13 µm CMOS technology. Compared with conventional current mode logic (CML) divider, the proposed split-load divider presents wider operating frequency range and lower power dissipation. The ratio of the locking range over the center frequency is up to 70% depending on the operating frequency. It consumes around 5mW power with 1.2V supply. The 8448 MHz PLL achieves phase noise of −92 dBc/Hz at frequency offsets of 100 kHz and has a reference spur of -56 dB with the second order passive low pass filter. The whole circuit (without test buffer) consumes only 13mA for a 1.2V power supply with die area of 0.9×1.3mm2.