Daniel Benoit

14nm FDSOI technology for high speed and energy efficient applications

This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m2 high-density bitcell and two 0.090°m2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.

Passivation issues in active pixel CMOS image sensors

Most of the integrated circuit industry follows a final passivation process which consists of a low temperature passivation layer deposition and a thermal anneal. This two step process is particularly relevant in CMOS imagers where the dark current is a major issue. This work shows that passivation material plays an important role in the device performance. We measured H diffusion through the final silicon nitride layer and we compare these results with the material properties and passivation efficiency.

Refined electrical analysis of two charge states transition characteristic of ¿borderless¿ silicon nitride.

Abstract In this paper we evaluate the electrical properties of silicon nitride so called “borderless nitride” deposited by PECVD process in the pre metal dielectric stack. Thus metal/silicon nitride/semiconductor structures have been analysed by an original electrical characterization based on C ( V ) and I ( V ) hysteresises. The objective is to understand how this material, initially introduced as etch stop layer and contaminant diffusion barrier, can impact active device performances. It appears that silicon nitride contains a huge defect quantity characterized in a non steady state and strongly influenced by maximum voltage applied. These charges can be balanced between either positive and negative states and are suspected to be K centers defects existing under two paramagnetic states K + and K − . In addition, a RF power variation of SiH 4 /NH 3 ratio, giving refractive indexes from 1.94 to 2.77, have shown that flatband voltage shift decreases with [Si]/[N] ratio whereas leakage current increases.

Study of stress in tensile nitrogen-plasma-treated multilayer silicon nitride films

The authors conducted a physico-chemical analysis of tensile sequential-nitrogen-plasma-treated silicon nitride films, which function as stressor liners in complementary metal oxide semiconductor (CMOS) technologies. These films are made of stacked nanometer-thick, plasma-enhanced, chemical vapor-deposited layers which were individually treated with N2-plasma, to increase stress. This study allowed us to monitor the evolution of the films’ chemical composition and stress as a function of process parameters such as deposition and post-N2-plasma duration. Consistent with secondary ion mass spectroscopy (SIMS), transmission electron microscopy (TEM) and other physico-chemical analysis results, it was shown that the elementary component of the films can be modeled with a bi-layer consisting of an untreated slice at the bottom that is covered by a more tensile post-treated film. In addition, we observed that longer plasma treatments increase residual stress, SiN bond concentration and layer density, while redu...

Reliable 3D damascene MIM architecture embedded into Cu interconnect for a Ta 2 O 5 capacitor record density of 17 fF/μm 2

A new simple 3D Damascene architecture requiring only one additional mask is introduced for high-density MIM capacitors. TiN/Ta₂O₅/TiN stack deposited by PEALD has been integrated between Cu interconnect levels to maximize quality factor Q, reaching up to 17 fF/μm² capacitance. High-performance, breakdown voltages over 15 V and good linearity, C₁ = 76 ppm/V and C₂ = 63 ppm/V² at 100 kHz, make this capacitor an unique solution for analog and RF applications embedded in Cu BEOL.

Impact of TaN/Ta copper barrier on full PEALD TiN/Ta2O5/TiN 3D damascene MIM capacitor performance

MIM capacitors are widely integrated for RF and analog applications. A high density full PEALD TiN/Ta2O5/TiN capacitor is integrated among copper interconnect following an innovative 3D damascene architecture. The impact of a TaN/Ta layer, introduced to avoid Cu diffusion, on both TiN electrode properties and integrated MIM stack performance is studied. Unexpected lower current was obtained without the barrier layer. As a result, up to 17 fF/mum2 capacitance densities were achieved with breakdown voltage over 15 V and excellent voltage linearity.

Combining high-resolution X-ray reciprocal space mapping and dark-field electron holography for strain analysis in 20 nm pMOS structures

In this paper we explore the benefit of combining High Resolution X-Ray Reciprocal Space Mapping (HR-RSM) and Dark-Field Electron Holography (DFEH) techniques for strain characterization of thin pMOS-like structures. We are able to simulate the measured HR-RSM from the displacement field extracted by DFEH. This is a first step developing High Resolution X-Ray Diffraction (HRXRD) as a viable technique for in-line strain metrology.

Contact etch stop a-SixNy:H layer: A key factor for single polysilicon flash memory data retentiona)

The silicon nitride (a-SixNy:H) contact etch stop layer strongly affects data retention performances in single polysilicon nonvolatile memories by acting on the initial charge loss phenomenon. Its improvement has required an analysis of influent plasma enhanced chemical vapor deposition process parameters through a design of experiment approach. The a-SixNy:H physico-electrical analysis points out that silicon rich compositions especially of its interfacial layer must be avoided to reduce a-SixNy:H charge amount and as a result to improve the data retention. Indeed, the a-SixNy:H being near the floating gate, its charges modulation could act as a parasitic memory screening charges stored in the floating gate by capacitive effects.

Impact of silicon nitride CESL on NLDEMOS transistor reliability

Aging of the linear drain current during OFF stress on a N-type lateral drain extended MOS is shown to be induced by the amorphous silicon nitride Contact Etch Stop Layer (CESL). A design of experiment on its PECVD conditions enables to demonstrate that the higher its Si-rich composition or at least of its interface, the higher the degradation. Supported by TCAD simulations, we propose a charge displacement model in the CESL that leads to the depletion of the extended drain region during stress explaining the on-resistance increase monitored by the linear drain current.

Integrated SiN on SOI dual photonic devices for advanced datacom solutions

We report on the co-integration of an additional passive layer within a Silicon Photonic chip for advanced passive devices. Being a CMOS compatible material, Silicon Nitride (SiN) appears as an attractive candidate. With a moderate refractive index contrast compared to SOI, SiN based devices would be intrinsically much more tolerant to fabrication errors while keeping a reasonable footprint. In addition, its seven times lower thermo-optical coefficient, relatively to Silicon, could lead to thermal-tuning free components. The co-integration of SiN on SOI has been explored in ST 300mm R and D photonic platform DAPHNE and is presented in this paper. Surface roughness of the SiN films have been characterized through Atomic Force Microscopy (AFM) showing an RMS roughness below 2nm. The film thickness uniformity have been evaluated by ellipsometry revealing a three-sigma of 21nm. Statistical measurements have been performed on basic key building blocks such as SiN strip waveguide showing propagation loss below 0.7dB/cm and 40μm radius bends with losses below 0.02dB/90°. A compact Si-SiN transition taper was developed and statistically measured showing insertion losses below 0.17dB/transition on the whole O-band wavelength range. Moreover, advanced WDM devices such as wavelength-stabilized directional couplers (WSDC) have been developed.