Jeffrey P. Mayhew

Layout design methodologies for sub-wavelength manufacturing

In this paper, we describe new types of layout design constraints needed to effectively leverage advanced optical wafter lithography techniques. Most of these constraints are dictated by the physics of advanced lithography processes, while other constraints are imposed by new photomask techniques. Among the methods discussed are 1) phase shift mask (PSM) lithography in which phase information is placed to the photomask in combination with conventional clear and dar information; 2) optical proximity correction (OPC) where predictable distorations in feature geometry are corrected by putting an inverse distortion on the mask; 3) off-axis illumination optics that improve resolution of some configurations at the expense of others; and 4) use of non-resolving assist features that improve neighboring structures.

OPC strategies to minimize mask cost and writing time

As k1 factors decline, optical proximity correction (OPC) treatments required to maintain dimensional tolerances involve increasingly complex correction shapes. This translates to more detailed, larger mask pattern databases. Intricate, dense mask-layouts increase mask writing time and cost. OPC employment within a growing number of lithography layers compounds the issue, leading to skyrocketing mask-set costs and long turn-times. ASIC manufacturing, where average chip life cycles consume less than 500 wafers, is particularly hard hit by elevated mask manufacturing costs. OPC increases mask data mainly by adding geometric detail - serifs, hammerheads, jogs, etc - to the design layout. The vertex count, a measure of shape complexity, typically expands by a factor of 2 to 5, depending on OPC objectives and accuracy requirements. OPC can also increase hierarchic data file size through loss of hierarchic compression. In this paper we outline several alternatives for reducing OPC data base size and for making OPC layout configurations friendlier to mask fabrication tools. An underlying assumption is that there is an optimum OPC treatment dictated by the behavior of the process, and that approximations to this ideal involve trade-offs with OPC accuracy. To whatever extent OPC effectiveness can be maintained while accuracy is compromised, mask complexity can be reduced.

Improvements in model-based assist feature placement algorithms

Demanding process window constraints have increased the need for effective assist feature placement algorithms that are robust and flexible. These algorithms must also allow for quick ramp up when changing nodes or illumination conditions. Placement based on the optical components of real process models has the potential to satisfy all of these requirements. We present enhancements to model-based assist feature algorithms. These enhancements include exploration of image-processing techniques that can be exploited for contact-via AF placement, model-based mask rule check (MRC) conflict resolution, the application of models to line-space patterns, and a novel placement technique for contact-via layers using a specially-built single modeling kernel.

Enriching design intent for optimal OPC and RET

In typical rule- or model-based optical proximity correction (OPC) the goal is to align the silicon layout edges as closely as possible to the corresponding edges in the design layout. OPC precision requirements are approaching 1nm or less at the 0.1mm process node. While state-of-the-art OPC tools are capable of operating at this accuracy, such tight requirements increase computational cycle time, output file size, and photomask fabrication cost. Accuracy requirements on different features in the design may vary widely, and regions that do not need the highest accuracy can be exploited to reduce OPC complexity. For example, transistor gate dimensions require tighter dimensional control than interconnect features on the polysilicon layer. Furthermore gate features typically occupy less area than interconnect. When relaxed OPC accuracy requirements are applied to the interconnect features, but not the gate features, the overall complexity of the polysilicon mask pattern can be significantly reduced without losing accuracy where it counts.

Assist feature placement analysis using focus sensitivity models

Sub-Resolution Assist Features (SRAFs) are placed into patterns to enhance the through process imaging performance of critical features. SRAFs are typically placed using complex rules to achieve optimal configurations for a pattern. However, as manufacturing process nodes are growing increasingly complex, the SRAF placement rules will most likely be unable to produce optimal performance on some critical features. A primary impediment to resolving these problems is identifying poorly performing features in an efficient manner. A new process model form referred to as a Focus Sensitivity Model (FSM) is capable of rapidly analyzing SRAF placement for through process pattern performance. This study will demonstrate that an FSM is capable of finding suboptimal SRAF placements as well as missing SRAFs. In addition, the study suggests that the FSM does not need to comprehend the entire photolithography process to analyze SRAF placement. This results in simpler models that can be generated before a manufacturing process enters its development phase.

Hybrid AAPSM compliance methodology to ensure design for manufacturing

Dark field Alternating Aperture Phase Shift Mask (AAPSM) technology has developed into an enabling Resolution Enhancement Technology (RET) in the sub-100nm semiconductor device era. As phase shift masks are increasingly used to resolve features beyond just the most critical (for example transistor gates on the poly layer) the probability of phase conflicts (same phase across a feature) has increased tremendously. It has become imperative to introduce design practices that enable the semiconductor fabrication to take advantage of the improved performance that AAPSM delivers. In this paper we analyze the different causes for phase conflicts and the appropriate methods for detecting them, thus building the basis for the Hybrid AAPSM compliance flow. This approach leverages the strengths of existing DRC tools and the AAPSM conversion software. The approach is effective for minimizing the area penalty, thus very effective for density driven designs. By design, it is suited for custom or semi-custom layouts.

Programmable RET Mask Layout Verification

Emerging resolution enhancement techniques (RET) and OPC are dramatically increasing the complexity of mask layouts and, in turn, mask verification. Mask shapes needed to achieve required results on the wafer diverge significantly from corresponding shapes in the physical design, and in some cases a single chip layer may be decomposed into two masks used in multiple exposures. The mask verification challenge is to certify that a RET-synthesized mask layout will produce an acceptable facsimile of the design intent expressed in the design layout. Furthermore costs, tradeoffs between mask-complexity, design intent, targeted process latitude, and other factors are playing a growing role in helping to control rising mask costs. All of these considerations must in turn be incorporated into the mask layout verification strategy needed for data prep sign-off. In this paper we describe a technique for assessing the lithographic quality of mask layouts for diverse RET methods while effectively accommodating various manufacturing objectives and specifications. It leverages the familiar DRC paradigm for identifying errors and producing DRC-like error shapes in its output layout. It integrates a unique concept of “check figures” - layer-based geometries that dictate where and how simulations of shapes on the wafer are to be compared to the original desired layout. We will show how this provides a highly programmable environment that makes it possible to engage in “compound” check strategies that vary based on design intent and adaptive simulation with multiple checks. Verification may be applied at the “go/no go” level or can be used to build a body of data for quantitative analysis of lithographic behavior at multiple process conditions or for specific user-defined critical features. In addition, we will outline automated methods that guide the selection of input parameters controlling specific verification strategies.

Understanding the parameters for strong phase-shift mask lithography

In this paper we analyze selective alternating PSM synthesis and OPC modeling parameters, taking into account lithographic constraints to PSM conformance. The results shown include phase and trim regions size and shape impact on the images printed on wafers at optimum conditions and through focus, at ideal as well as in the presence of errors in phase and transmission due to mask manufacturing.