Daniel Guidotti

Accurate electrical simulation and design optimization for silicon interposer considering the MOS effect and eddy currents in the silicon substrate

In this paper, a group of coplanar lines on a silicon dioxide insulating layer on a nominally doped silicon substrate is simulated and measured. Electrical parameters extracted from published data are used and lead to substantially improved agreement with measurements. In addition, several models of redistribution layer (RDL) with different shape-TSVs (through silicon vias) are simulated, along with two different joint structures between TSV and RDL. Simulation result suggest that because the electrical length is very short reflection losses attributed to the structural details of the TSV may be ignored in the applicable frequency band of the TSV. In addition, several optimized transmission line structures are designed and simulated. Results suggest that design criteria used to optimize lines in organic substrates are not directly transferable to a silicon substrate. This paper shows a simple but effective method with which to analyze the influences exerted by the metal oxide semiconductor (MOS) capacitance at the TSV interface and eddy currents in the substrate on a transmission line. Finally, newly de-embedded test structures are provided to extract spice model parameters for TSV modeling.

Millimeter wave interchip communication

High performance multicore processors are approaching 256 GFLOPS and use and generate data at unprecedented rates. Much of the short range data transport between chips, however, is based on legacy LC transmission line infrastructure. Consequently, high performance, systems running memory intensive applications are able to utilize only a fraction of their available computational potential and remain idle for many clock cycles while waiting for data and instructions. A number of alternate short range transport technologies are listed in the International Technology Roadmap for Semiconductors, among which the most promising is inter-chip optical communication. This paper proposes that guided millimeter waves and high order digital modulation can be an effective alternate method by which processors and memory can exchange information with unprecedented bandwidth, power efficiency and I/O density competitiveness.

Low latency high throughput memory-processor interface

Scaling to ExaFLOPS computing, or 100 times faster than the present version of the Fujitsu K-supercomputer, presents well known challenges, among which are power dissipation, memory capacity and access bandwidth, data locality and fault tolerance. The optimum Amdahls speed-up strategy is multi faceted, with greater memory bandwidth and lower access latency being generally recognized as areas to improve. To this end, evolutionary compute node architecture is considered based on a multichip interposer platform and a millimeter wave memory interface. The interposer serves as the compute node physical platform and wiring distribution layer connecting the chip multiprocessor (CMP) with on-interposer memory to an organic board. For example, the interposer may be composed of glass to reduce through-via parasitic and support one multi-GFLOPS CMP with sufficient on-interposer DRAM for balanced operation. The memory interface consists of dense arrays of millimeter waveguide with integrated mm wave transceivers and should support 40 Gb/s per channel for an aggregate throughput of 1 TB/s with estimated latency of 10-15 clock cycles. This paper examines channel impediments, design and construction. Data transmission on a 72 GHz carrier frequency and 12 Gb/s OOK modulation will be presented at the conference if available.

The electrical design of high-speed and high-density ASIC package

This paper introduces a package of a high-speed and high-density switching ASIC with over 1000 pins and hundreds of high-speed transmission lines crowded in two layers of the substrate, and also demonstrates Signal Integrity (SI) and Power Integrity (PI) implementation. In order to route the transmission lines with minimum distortion, crosstalk and attenuation, routing is co-designed with die and BGA maps. To guarantee that over a hundred transmission lines will be matched identically, each transmission line is designed to have a corresponding continuous return path routed among integrated copper shapes. Various routing schemes designed to take advantage of the physical and electrical performance of materials and structures are also implemented to optimize the performance of the transmission line. Various simulations are carried out on test segments to evaluate performance and signal integrity in the frequency and time domains.

Nonlinear thermal stress & strain analysis of through silicon vias with different structures and polymer filling

Due to the differences in the thermal expansion coefficients of copper and silicon, a large thermal stress develops at the interface between a Cu-filled via and both the insulation layer and the surrounding silicon when the structure is subjected to temperature loading. In this paper four TSV geometries are considered in an effort to investigate the role of via geometry on stress relief. Thermo-mechanical finite element method (FEM) simulation software is used to analyze the influence of TSV shape on the nonlinear thermal stresses and strains generated under temperature cycling. The height (H) and radius (D) of a via are varied in the simulations in order to evaluate the magnitude and distribution of the thermal stress. In addition, various insulation materials and thicknesses are also considered in order to evaluate their thermo-mechanical behaviors. Thermal stress decreases with increasing SiO2 insulator thickness up to the process maximum of 1 um. In the case of Parylene, when the insulator thickness is less than 5 um, the stress value decreases to minimum for a polymer thickness of 5 um, thereafter increases showing an optimal thickness for minimum thermal stress. Finally, the vias with polymer filling are simulated.

Three-dimensional PN junction capacitor for passive integration

A wafer level three-dimensional (3D) PN junction capacitor for passive device integration on Si is developed. The 3D capacitor structure is created by deep trench etching of Si and appropriate doping. The salient characteristics of the PN junction capacitors fabricated in this study are as follows. The maximum areal capacitance density is 11.5 fF/μm2, the highest breakdown voltage is −20 V, and the minimum leakage current is 5 nA at an applied reverse voltage of −5 V. In comparison with the planar PN junction capacitor, the 3D junction capacitor can provide 8-12 times the capacitance density at the same doping concentration.

A study of high-density embedded capacitor for silicon-substrate package

Rapidly growing performance and mixed-signal integration is driving the need for product component miniaturization in electronics applications. Embedded passive technology is a potentially attractive solution to replace discrete passives. Embedded capacitors are widely used for broad range of applications including filtering, tuning and power-bus decoupling in the substrate. Micro-Electron-Mechanical System (MEMS) process based on silicon and deep etching 3D patterns on silicon substrate is used. The fabrication process and properties of a semiconductor decoupling capacitor with high capacitance density is reported in this paper. Measurement results indicate that the capacitance density can reach 12nF/mm2, which is 10–12 times that planar semiconductor capacitors, and that the decoupling frequency range is between from 10MHz to 3.2GHz.

A low-power wide-band 20GHz VCO in 65nm CMOS

A 20GHz (centralized at 18.7GHz) voltage controlled oscillator (VCO) is implemented in standard 65nm CMOS technology. In the design process, several design optimizations including tail current source, cross-couples dimension and inductor selection, are done to achieve a good performance without additional area requirement. Through these techniques, the measured phase noise of -98dBc/Hz@1MHz achieved at 19.97 GHz and the figure of merit (FOM) is -176dBc/Hz. With the help of digital controlled switch array, tuning range is about 15%, from 17.36 to 20.15 GHz without much performance degradation. The total current is 4.6mA under the 1.3V supply voltage, including the buffer current consumption of 0.9mA. To our best knowledge, this is the minimum current consumption for VCO in this frequency band. The area of the core circuit is only 0.35 × 0.25mm2.

Signal integrity design and validation for multi-GHz differential channels in SiP packaging system with eye diagram parameters

Differential interconnect lines in multi-gigabits system in package (SiP) packaging system are studied in this paper. The performance of interconnect lines can be easily estimated with jitter and eye opening using the eye diagram that is very helpful metric. To maintain good eye-diagram with high voltage swing and low timing jitter, a signal integrity (SI) design flow of SiP is proposed based on eye-diagram parameters. To validate the influences of SI design to eye-diagrams, the relationship between the parameters of eye diagram and the structures of the impedance discontinuities physical elements such as vias, SMT pads are studied by a combination of software simulation and hardware validation. Some SI design rules are stipulated. As an example, a 4-channel × 10Gbp/s/channel optical transceiver in an SiP package is designed.

Electrical design of high density low cost package for a switch ASIC

A switch Application Specific Integrated Circuit (ASIC) chip implemented in six-substrate layers for low cost design which has more than 1000 pin-count. This paper deals with the electrical design of the high density package, including transmission characteristics of the key signal lines, crosstalk between signal lines, the coupling between neighboring power pins, DC IR drop and AC input impedance etc.. The authors used different local grounding solutions to reduce the current density and the coupling between power pins. In this paper, wide copper traces/shapes on the substrate layers were used to achieve minimum DC resistance and suppress the crosstalk between layers. Both wide copper traces/shapes and smallest available surface mount technology (SMT) capacitors placed at the bottom of the substrate were used to minimize the input impedance of power supply networks. Electrical test, DFT test and functional test showed that the low cost package meets the design requirements.