Daniel Lizzit

Analysis of the Performance of n-Type FinFETs With Strained SiGe Channel

This paper reports a simulation study investigating the drive current of a prototypical SiGe n-type FinFET built on a relaxed SiGe substrate for different values of the Ge content x in the Si(1-x)Gex active layer. To this purpose, we performed strain simulations, band-structure calculations, and multisubband Monte Carlo transport simulations accounting for the effects of the Ge content on both the band-structure and the scattering rates in the transistor channel. Our results suggest that the largest on-current may be obtained with a simple Si active layer, because of the beneficial strain induced by the SiGe substrate. A SiGe channel instead is less performing because of strain relaxation and alloy scattering.

A new formulation for surface roughness limited mobility in bulk and ultra-thin-body metal–oxide–semiconductor transistors

This paper presents a new model for the surface roughness (SR) limited mobility in MOS transistors. The model is suitable for bulk and thin body devices and explicitly takes into account the non linear relation between the displacement Δ of the interface position and the SR scattering matrix elements, which is found to significantly influence the r.m.s value (Δrms) of the interface roughness that is necessary to reproduce SR-limited mobility measurements. In particular, comparison with experimental mobility for bulk Si MOSFETs shows that with the new SR scattering model a good agreement with measured mobility can be obtained with Δrms values of about 0.2 nm, which is in good agreement with several AFM and TEM measurements. For thin body III–V MOSFETs, the proposed model predicts a weaker mobility degradation at small well thicknesses (Tw), compared to the Tw6 behavior observed in Si extremely thin body devices.

Surface roughness limited mobility modeling in ultra-thin SOI and quantum well III-V MOSFETs

This paper presents a new model for the surface roughness (SR) limited mobility (μSR). The model is suitable for bulk, for ultra thin body (UTB) and for Hetero-Structure Quantum Well (HS-QW) MOSFETs. Comparison with experimental mobility for Si bulk MOSFETs shows that a good agreement with measured mobility can be obtained with a r.m.s. value of the SR spectrum close to several AFM and TEM measurements. For III-V MOSFETs with small well thickness the proposed model shows a weaker mobility degradation with respect to the Tw6 behavior.

Performance Benchmarking and Effective Channel Length for Nanoscale InAs, , and sSi n-MOSFETs

Thanks to the high electron velocities, III-V semiconductors have the potential to meet the challenging ITRS requirements for high performance for sub-22-nm technology nodes and at a supply voltage approaching 0.5 V. This paper presents a comparative simulation study of ultrathin-body InAs, In0.53Ga0.47As, and strained Si MOSFETs, by using a comprehensive semiclassical multisubband Monte Carlo (MSMC) transport model. Our results show that: 1) due to the finite screening length in the source-drain regions, III-V and Si nanoscale MOSFETs with a given gate length (LG) may have a quite different effective channel length (Leff); 2) the difference in Leff provides a useful insight to interpret the performance comparison of III-V and Si MOSFETs; and 3) the engineering of the source-drain regions has a remarkable influence on the overall performance of nanoscale III-V MOSFETs.

Performance projection of III-V ultra-thin-body, FinFET, and nanowire MOSFETs for two next-generation technology nodes

Using state-of-the-art simulation tools ranging from semi-classical Monte-Carlo to full-quantum atomistic approaches, the competitiveness of III-V compounds for next-generation high-performance logic switches is confirmed. A planar double-gate ultra-thin-body (DG-UTB), a triple-gate FinFET, and a gate-all-around nanowire (NW) transistor have been designed according to the ITRS specifications for two technology nodes with physical gate lengths of Lg=15 nm and 10.4 nm. A thorough performance comparison of digital and analog figures of merit at these nodes reveals that for Lg=15 nm, the performance of planar and 3-D architectures is comparable. At LG=10.4 nm, the III-V NW promises the highest performance, especially when lowering the supply voltage from 0.59 V to 0.50 V. It also significantly outperforms its strained silicon counterpart. Finally, the effects of series resistance combined with interface traps, surface roughness, alloy scattering, and electron-phonon interactions have been found to deteriorate the III-V ballistic ON-current by 50–60%.

An Improved Surface Roughness Scattering Model for Bulk, Thin-Body, and Quantum-Well MOSFETs

This paper reports about the implementation in a multisubband Monte Carlo device simulator of a comprehensive surface roughness scattering model, based on a nonlinear relation between the scattering matrix elements and the fluctuations Δ(r) of the interface position. The model is first extended by including carrier screening effects and accounting for scattering at multiple interfaces, and it is then used for the analysis of relevant experimental data sets. We show that the new model can reproduce fairly well the silicon universal mobility curves as well as mobility data for ultrathin-body InGaAs MOSFETs using Δrms values consistent with atomic force microscopy (AFM) and TEM measurements. Our simulation results and some experimental data also indicate that mobility in InGaAs MOSFETs is reduced with decreasing well thickness, TW, with a weaker dependence compared with the TW6 behavior observed in Si devices.

Simulation analysis of III–V n-MOSFETs: Channel materials, Fermi level pinning and biaxial strain

In this work we employ a state-of-the-art Multi-Subband Monte Carlo simulator to investigate the performance of III-V n-MOSFETs with LG = 11.7nm. We analyze GaSb versus InGaAs strained and unstrained channel materials and the implications of Fermi level pinning on electrostatic and transport. We found that InGaAs MOSFETs can outperform strained silicon for low VDD applications. Advantages related to strained InGaAs are limited and mainly due to reduced Fermi Level Pinning.

Toward computationally efficient Multi-Subband Monte Carlo simulations of nanoscale MOSFETs

We show how intense exploitation of multi-core architectures allowed us to cut by up to an order of magnitude the execution times of a Multi-Subband Monte Carlo (MSMC) simulator. The result brings simulations with the MSMC method out of the strictly academic domain and close to the execution time threshold for effective use in R&D departments of semiconductor research centres and industries.

The impact of interface states on the mobility and the drive current of III-V MOSFETs

We investigate the effect of interface states at the channel/insulator interface of III-V MOSFETs by means of accurate Schrödinger-Poisson and Multi-subband Monte Carlo simulations. Traps in the conduction band are found to be the main responsible of the Fermi level pinning observed in the experiments. These traps impact the mobility measurements as well as the current drive of short channel devices.

Surface roughness limited mobility in multi-gate FETs with arbitrary cross-section

This paper presents the derivation, implementation and validation of a new model for Surface Roughness Scattering (SRS) in multi-gate FETs (MuGFETs) and gate-all-around nanowires (GAA-NW) FETs. The model employs a non linear relation between SRS matrix elements and interface fluctuations, that in planar MOSFETs allowed us to reconcile mobility simulations with experimental values for the r.m.s. interface roughness Δτη8 [1], [2]. The model is formulated for fairly arbitrary cross-sections and biasing conditions.