Patrik Osgnach

Performance Benchmarking and Effective Channel Length for Nanoscale InAs, , and sSi n-MOSFETs

Thanks to the high electron velocities, III-V semiconductors have the potential to meet the challenging ITRS requirements for high performance for sub-22-nm technology nodes and at a supply voltage approaching 0.5 V. This paper presents a comparative simulation study of ultrathin-body InAs, In0.53Ga0.47As, and strained Si MOSFETs, by using a comprehensive semiclassical multisubband Monte Carlo (MSMC) transport model. Our results show that: 1) due to the finite screening length in the source-drain regions, III-V and Si nanoscale MOSFETs with a given gate length (LG) may have a quite different effective channel length (Leff); 2) the difference in Leff provides a useful insight to interpret the performance comparison of III-V and Si MOSFETs; and 3) the engineering of the source-drain regions has a remarkable influence on the overall performance of nanoscale III-V MOSFETs.

An Improved Surface Roughness Scattering Model for Bulk, Thin-Body, and Quantum-Well MOSFETs

This paper reports about the implementation in a multisubband Monte Carlo device simulator of a comprehensive surface roughness scattering model, based on a nonlinear relation between the scattering matrix elements and the fluctuations Δ(r) of the interface position. The model is first extended by including carrier screening effects and accounting for scattering at multiple interfaces, and it is then used for the analysis of relevant experimental data sets. We show that the new model can reproduce fairly well the silicon universal mobility curves as well as mobility data for ultrathin-body InGaAs MOSFETs using Δrms values consistent with atomic force microscopy (AFM) and TEM measurements. Our simulation results and some experimental data also indicate that mobility in InGaAs MOSFETs is reduced with decreasing well thickness, TW, with a weaker dependence compared with the TW6 behavior observed in Si devices.

Simulation analysis of III–V n-MOSFETs: Channel materials, Fermi level pinning and biaxial strain

In this work we employ a state-of-the-art Multi-Subband Monte Carlo simulator to investigate the performance of III-V n-MOSFETs with LG = 11.7nm. We analyze GaSb versus InGaAs strained and unstrained channel materials and the implications of Fermi level pinning on electrostatic and transport. We found that InGaAs MOSFETs can outperform strained silicon for low VDD applications. Advantages related to strained InGaAs are limited and mainly due to reduced Fermi Level Pinning.

Toward computationally efficient Multi-Subband Monte Carlo simulations of nanoscale MOSFETs

We show how intense exploitation of multi-core architectures allowed us to cut by up to an order of magnitude the execution times of a Multi-Subband Monte Carlo (MSMC) simulator. The result brings simulations with the MSMC method out of the strictly academic domain and close to the execution time threshold for effective use in R&D departments of semiconductor research centres and industries.

The impact of interface states on the mobility and the drive current of III-V MOSFETs

We investigate the effect of interface states at the channel/insulator interface of III-V MOSFETs by means of accurate Schrödinger-Poisson and Multi-subband Monte Carlo simulations. Traps in the conduction band are found to be the main responsible of the Fermi level pinning observed in the experiments. These traps impact the mobility measurements as well as the current drive of short channel devices.

State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors

We review the Monte Carlo method to model semi-classical carrier transport in advanced semiconductor devices. We report examples of the use of the Multi-Subband Monte Carlo method to simulate MOSFETs with III-V compound semiconductor channel. Monte Carlo transport modeling of graphene-based transistors is also addressed.

Performance study of strained III–V materials for ultra-thin body transistor applications

A comprehensive description of band gap and effective masses of III-V semiconductor bulk and ultra-thin body (UTB) structures under realistic biaxial and uniaxial strain is given using numerical simulations from four different electronic structure codes. The consistency between the different tools is discussed in depth. The nearest neighbor sp3d5s* empirical tight-binding model is found to reproduce most trends obtained by ab initio Density Functional Theory calculations at much lower computational cost. This model is then used to investigate the impact of strain on the ON-state performance of realistic In0.53Ga0.47As UTB MOSFETs coupled with an efficient method based on the well-known top-of-the-barrier model. While the relative variation of effective masses between unstrained and strained cases seems promising at first, the calculations predict no more than 2% performance improvement on drive currents from any of the studied strain configurations.

Quasi-Ballistic

We carefully scrutinize the potential of ultrathin body strained (111) GaAs MOSFETs to achieve better performance than other GaAs-based channel FETs at scaled channel length and with relaxed thickness requirements, thanks to L-valleys enhanced density-of-states (DoS) and carrier transport. Calibrated multi-subband Monte Carlo simulations including scattering provide the modeling framework necessary for accurate simulations. The results show that L-valley-enhanced transport most likely will not yield the ION and switching time improvements observed in simple ballistic simulations, even if considering the ideal material properties and purely phonon scattering limited transport. In fact, the increased DoS and inversion charge at the virtual source provided by the L-valleys in the strained material is counterbalanced by an increased phonon scattering rate and reduced carrier velocity.

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Thanks to the high electron velocities, III-V semiconductors have the potential to meet the challenging ITRS requirements for high performance for sub-22-nm technology nodes and at a supply voltage approaching 0.5 V. This paper presents a comparative simulation study of ultrathin-body InAs, In0.53Ga0.47As, and strained Si MOSFETs, by using a comprehensive semiclassical multisubband Monte Carlo (MSMC) transport model. Our results show that: 1) due to the finite screening length in the source-drain regions, III-V and Si nanoscale MOSFETs with a given gate length (LG) may have a quite different effective channel length (Leff); 2) the difference in Leff provides a useful insight to interpret the performance comparison of III-V and Si MOSFETs; and 3) the engineering of the source-drain regions has a remarkable influence on the overall performance of nanoscale III-V MOSFETs.

- and L-Valleys Transport in Ultrathin Body Strained (111) GaAs nMOSFETs

We investigate the operation and performance of planar SiGe/Si and In_0.53Ga_0.47As/In_0.7Ga_0.3As/In_0.53Ga_0.47As hetero-junction Semiconductor on Insulator (ScOI) Tunnel FET (TFET) devices. The alignment between the hetero-junction, the gate edge and the source junction is systematically shifted to search for the highest ON-current and the lowest Subthreshold Swing (SS). A slight positive misalignment between the hetero-junction and the metallurgical junction is beneficial to improve I_ON but for the considered devices the ON-current at V_DD=0.5V and I_oFF=1pA/μm hardly exceeds 1μA/μm. Furthers reduction of the band gap by lattice strain appears mandatory to exceed this limit in the explored material systems.