Egor Sogomonyan

Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs

In this article we propose a structure dependent method for the systematic design of combinational selftesting fault detection circuits that is well adapted to the arbitrarily chosen technical fault model. According to the fault model considered the outputs of the circuit are partitioned into different generally nondisjoint groups of weakly independent outputs. The parities of these groups of weakly independent outputs are compared in test mode as well as in normal operation mode with the corresponding predicted parities by use of a self-checking checker. For on-line detection, the hardware is in normal operation mode, and for testing, it is in test mode. In the test mode, these fault detection circuits guarantee a 100% fault coverage for single stuck-at-0/1 faults and a high fault coverage for arbitrary faults. In normal operation mode all technical faults considered will be detected possibly, with some degree of latency.

Multimode scan: Test per clock BIST for IP cores

Built-in self-test (BIST) is an attractive design-for-test methodology for core-based SoC design because of the minimal need for test access when tests are generated and evaluated within the core itself. However, the scan based logic BIST approach being widely considered for this application suffers from two significant weaknesses: slow test-per-scan execution, and a limited capability for detecting realistic timing and delay faults, critical in deep submicron technologies. The new multimode scan based approach presented here supports test-per-clock BIST, which runs orders of magnitude faster, and also provides significantly better delay fault coverage.

Testability evaluation of sequential designs incorporating the multi-mode scannable memory element

The Multi-Mode Scannable Memory Element (MSME) is a design-for-test technique that combines the testing efficiency of the Circular Self-Test Path approach with a full scan capability to support custom test vectors, diagnosis, and design debugging. A key feature is the ability to support pseudorandom at-speed delay testing of the functional circuit paths without imposing any performance penalty on the design beyond that for traditional scan. This paper presents a CMOS design for the MSME, and investigates benchmark circuits designed with this memory element. The results show that very high stuck-at and transition delay test coverage can be achieved for most cases using the pseudorandom self-test mode alone. Evaluation of layouts indicates low to moderate area overhead.

A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST

In this paper a joint implementation of a parity preserving multi-input signature analyzer (PMISA) and a parity checker is described. The PMISA simultaneously can be used for concurrent checking and for testing of digital circuits. In the case of concurrent checking errors are detected by their erroneous parity. If a circuit is tested errors are detected either by their erroneous parity or by the erroneous signature of the PMISA. A possible scan-mode of the PMISA allows its application in a scan path with parity-encoded inputs and outputs of the combinational modules which are driven by register sets. In normal operation mode all the registers of the PMISA can be utilized as functional registers of the combinational circuit.