Daniela Munteanu

A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications

The pseudo-MOS transistor (/spl Psi/-MOSFET) is a surprising and useful technique for the rapid evaluation of SOI wafers, prior to any CMOS processing. We review the static and dynamic modes of operation as well as the main models and methods for electrical parameter extraction. Selected numerical simulations are presented in order to clarify the optimal conditions of operation. Finally, practical applications are exemplified which illustrate the efficiency of the /spl Psi/-MOSFET technique for in situ characterization of SOI technologies and processes.

Generation-recombination transient effects in partially depleted SOI transistors: systematic experiments and simulations

A synthesis of the most frequent transient phenomena due to floating-body effects in partially depleted SOI MOSFETs is presented. The dominant physical mechanisms are examined through a variety of experiments. Comprehensive models which predict the transient effects are included in SOISPICE. Simulated transients involving both generation and recombination are fully validated by the experiments and are shown to he useful for reliable carrier lifetime extraction as well as SOI circuit simulation.

Experimental Investigation on the Quasi-Ballistic Transport: Part I—Determination of a New Backscattering Coefficient Extraction Methodology

A new fully experimental method to determine the backscattering coefficient and the ballistic ratio of n- and p-FDSOI and multigate nanodevices is proposed in this paper. This technique is the first one that takes multisubband population, carrier degeneracy, and short channel effects into account. Owing to self-consistent Poisson-Schrodinger simulations, common assumptions such as one subband occupied by carriers are investigated. For the first time, universal abaci, which are functional whatever the architecture dimensions and the gate/substrate polarizations, have been developed in order to accurately extract backscattering coefficients for n- and p-FDSOI MOSFETs, both in linear and saturated regimes.

Modeling of drain current overshoot and recombination lifetime extraction in floating-body submicron SOI MOSFETs

This work reports on a new general modeling of recombination-based mechanisms related to electrically floating-body partially-depleted (PD) SOI MOSFETs. The model describes drain current overshoots induced when turning on the transistor gate and suggests a novel extraction method for the recombination lifetime in the silicon film. We show that the recombination process associated with drain current overshoots in PD silicon-on-insulator (SOI) MOSFETs takes place mainly in the depletion region and not in the neutral region as in case of pulsed MOS capacitors. Associated with existing techniques for generation lifetime extraction, our model offers, for the first time, the possibility of complete and rapid characterization for both generation and recombination lifetime using drain current transients in floating-body SOI MOSFETs. The model is used in order to characterize submicron SOI devices, allowing a thorough investigation of technological parameters impact on floating-body-induced transient mechanisms.

Experimental Investigation on the Quasi-Ballistic Transport: Part II—Backscattering Coefficient Extraction and Link With the Mobility

Using a new extraction methodology taking into account multisubband population and carrier degeneracy, we have experimentally determined backscattering coefficients, ballistic ratios, and injection velocities of n- and p-FDSOI devices with gate lengths down to 30 nm in the saturated and, for the first time, in the linear regimes. The evolution of these quasi-ballistic parameters is examined as a function of the inversion charge in the channel and at temperatures ranging from 50 to 293 K, showing stronger ballistic ratios in the saturated regime than in the linear one. We particularly focus on the linear regime, and a model linking ballisticity ratios and effective mobility is proposed and validated experimentally for different gate lengths. According to the experimental evaluation of the device mean-free path and its evolution with both the inversion charge in the channel and the temperature, we investigate the mobility degradation with decreasing gate lengths, highlighting the importance of Coulomb scattering on this unexpected mobility behavior.

Detailed characterization of Unibond material

Abstract Unibond wafers are evaluated by optical, physical (TEM, AFM, X-ray), chemical (Secco and HF etch), and electrical (Ψ-MOSFET, Hall, μ-PCD) methods. The low density of defects, the high quality of oxide and interfaces, and the excellent electrical properties (carrier mobility and lifetime) are key properties. The parameters extracted from MOS test devices confirm that Unibond is a very suitable technology for thin-film CMOS circuits.

Investigation of SOI MOSFETs with ultimate thickness

Abstract Ultra-thin SOI MOSFETs with 1–5nm thick SOI film, are experimentally and theoretically investigated. Single- and double-gate configurations are compared; the double-gate MOSFET exhibits a substantial increase in transconductance, presumably resulting from volume inversion. Most of the experimental data can be explained by combining classical models with self-consistent quantum calculations. The characteristics are well-behaved and reveal unique “ultra-thin” film properties: enhanced interface coupling and body-substrate coupling, degraded mobility, increased threshold voltage.

A new lifetime characterization technique using drain current transients in SOI material

A new technique based on the transient operation of the pseudo-MOS transistor is proposed for direct evaluation of generation lifetime and surface velocity in SOI wafers. The main advantages of the proposed technique are: (i) in situ operation (no prior processing of a transistor), (ii) set-up simplicity, (iii) fast comparison of different SOI technologies and (iv) simple identification of Si-film conductivity type. The influence of the electrical and non-electrical parameters of this technique is systematically investigated. Various SOI wafers (SIMOX and UNIBOND) are compared.

Soft errors : from particles to circuits

Foreword Preface Acknowledgments Authors Editor Introduction Glossary ENVIRONMENTS: DEFINITION AND METROLOGY Terrestrial Cosmic Rays and Atmospheric Radiation Background Primary Cosmic Rays Historical Background Extragalactic and Galactic Cosmic Rays (GCRs) Solar Wind and Solar Energetic Particles Magnetospheric Cosmic Rays Secondary Cosmic Rays in the Atmosphere and at Ground Level Development of Air Showers Modulation Factors of Particle Production in the Atmosphere and at Ground Level Radiation Environment at Ground Level (Particles, Flux, Variations, Shielding) Particle Fluxes at Sea Level Flux Variations Shielding Issues Synthesis Tools, Codes, and Models to Simulate Atmospheric and Terrestrial CRs SEUTEST EXPACS (PARMA Model) QARM CORSIKA PLANETOCOSMICS CRY References Detection and Characterization of Atmospheric Neutrons at Terrestrial Level: Neutron Monitors Neutron Monitors (NM) Historical Background Neutron Monitor Design and Operation Neutron Monitor Detection Response Plateau de Bure Neutron Monitor PdBNM Design PdBNM Installation and Operation Connection to the Neutron Monitor Database PdBNM Monte Carlo Simulation Concluding Remarks References Natural Radioactivity of Electronic Materials Radioactivity Radioactive Decay Alpha-Particle Emission Radioactive Nuclides in Nature Primordial Radionuclides Uranium Decay Chain Thorium Decay Chain Cosmic-Ray-Produced Radionuclides Radon Radionuclides and Radioactive Contamination in Advanced CMOS Technologies Alpha Radiation from Interconnect Metallization and Packaging Materials Emissivity Model Analytical Model for Monolayers Analytical Model for Multilayer Stack Universal Nomogram for Bulk Silicon References Alpha-Radiation Metrology in Electronic Materials Introduction Alpha-Particle Detection Techniques: Terms and Definitions Gas-Filled Counters Principle of Operation Ionization Counters Proportional Counters Ultralow-Background Alpha Counter Design and Operation of the UltraLo-1800 Signal Generation and Rejection Pulse and Event Classification Cosmogenics and Radon Issues Example of Measurements Multicenter Comparison of Alpha-Particle Measurements Other Techniques Silicon Alpha Detectors Liquid and Solid-State Scintillators ICP-MS and VPD ICP-MS References SOFT ERRORS: MECHANISMS AND CHARACTERIZATION Particle Interactions with Matter and Mechanisms of Soft Errors in Semiconductor Circuits Interactions of Neutrons with Matter Cross Section Types of Neutron-Matter Interactions Recoil Products Interaction of Thermal Neutrons with 10B Atmospheric Neutron-Silicon Interaction Databases Interactions of Charged Particles with Matter Ionization Stopping Power Range Alpha Particles Heavy Ions Electrons Interaction of Protons with Matter Interaction of Pions with Matter Interaction of Muons with Matter Basic Mechanisms of Single-Event Effects on Microelectronic Devices Charge Deposition (or Generation) Charge Transport Charge Collection SEU Mechanisms in Memories (Single-Bit Upset and Multiple-Cell Upset) SEE Mechanisms in Digital Circuits Sequential Logic Combinational Logic References Accelerated Tests Introduction Methodology and Test Protocols SEU Cross Section Test Equipment Requirements Test Plan Test Conditions Experiments Using Intense Beams of Particles High-Energy Neutrons Thermal Neutrons Protons Muons Alpha-Particle Accelerated Tests Using Solid Sources Evaluation of Various Neutron Broad-Spectrum Sources from a Simulation Viewpoint Simulation Details Nuclear Event Analysis Implications for the Soft-Error Rate References Real-Time (Life) Testing Introduction Real-Time Testing Methodology Instrumentation Issues Differentiation of the SER Components Statistics for RTSER: Typical Example Metrology of Atmospheric Neutron Flux Survey of a Few Recent RTSER Experiments IBM Intel Sony Tohoku University, Hitachi, and Renesas Electronics Cypress Xilinx NXP RTSER Experiments Conducted at ASTEP and LSM ASTEP and LSM Test Platforms RTSER Experiments Comparison with Accelerated Tests References SOFT ERRORS: MODELING AND SIMULATION ISSUES Modeling and Simulation of Single-Event Effects in Devices and Circuits Interest in Modeling and Simulation Main Approaches of Electrical Simulation at Device Level Main Simulation Approaches at Circuit Level Device-Level Simulation Transport Models Emerging Physical Effects TCAD Simulation Analytical and Compact Model Approaches Circuit-Level Simulation Approaches SPICE-Like Circuit Simulation Mixed-Mode Approach Full Numerical Simulation in the 3D Device Domain References Soft-Error Rate (SER) Monte Carlo Simulation Codes General-Purpose Monte Carlo Radiation-Transport Codes Review of Recent Monte Carlo Codes Dedicated to the SER Issue Intel Radiation Tool (IRT) PHITS-HyENEXSS Code System TIARA-G4 Detailed Description of the TIARA-G4 Code Circuit Architecture Construction Module Radiation-Event Generator Interaction, Transport, and Tracking Module SRAM Electrical-Response Module Soft-Error Rate Calculation Module Experimental versus Simulation Results: Discussion Impact of Thermal and Low-Energy Neutrons on a 40 nm SRAM Circuit Comparison between TIARA and TIARA-G4: Impact of the BEOL on the SER SER Estimation of a 65 nm SRAM under High-Energy Atmospheric Neutrons Effects of Low-Energy Muons on a 65 nm SRAM Circuit References SOFT ERRORS IN EMERGING DEVICES AND CIRCUITS Scaling Effects and Their Implications for Soft Errors Introduction Feature-Size Scaling Geometric Scaling Ion-Track Spatial Structure versus Device Dimensions Carrier Channeling in Wells and Electrical Related Effects Variability and SEE Critical Charge Increasing Sensitivity to Background Radiation Low-Energy Protons Atmospheric Muons Low-Alpha-Material Issue Trends and Summary for Ultrascaled Technologies References Natural Radiation in Nonvolatile Memories: A Case Study Introduction Flash Memory Architectures and Electrical Operation NOR Architecture NAND Architecture Radiation Effects in Floating-Gate Memories Modeling and Simulation of Nonvolatile Memories Using TIARA-G4 Platform Description of TIARA-G4 NVM Platform Physical Model Considered Simulation Results Experimental Characterization Experimental versus Simulation Results: Discussion References SOI, FinFET, and Emerging Devices Introduction Silicon-on-Insulator (SOI) Technologies SEE Mechanisms in SOI Technologies 3D Simulation Study of Radiation Response of 50 nm FDSOI Devices SEU Sensitivity of FDSOI SRAM Cells Multiple-Gate Devices Impact of Quantum Effects Transient Response of Multiple-Gate Devices Radiation Hardness of Circuits Based on Multiple-Gate Devices Bulk and SOI FinFET Multichannel Architectures with Multiple-Gate Devices Multiple-Gate and Multichannel Devices with Independent Gates Simulation Details FinFET Devices MC-NWFET Devices Comparison between FinFET and MC-NWFET Devices Junctionless Devices Simulation Details Radiation Sensitivity of Individual Devices SEU Sensitivity of SRAM Cells III-V FinFET and Tunnel FET References

Numerical simulation of the pseudo-MOSFET characterization technique

Abstract The Ψ-MOSFET offers the most appropriate method for detailed electrical characterization of bare silicon on insulator (SOI) wafers. 2-D and 3-D numerical simulations of the Ψ-MOSFET are performed in order to validate the basic principles and to uncover several less obvious aspects: evaluation of the geometrical factor, distribution of the current lines, influence of the sample size and borders proximity. The optimal conditions for accurate operation of the Ψ-MOSFET are clarified in terms of sample dimensions, probe interdistance, film thickness and contact area.