S. Sauze

Altitude and Underground Real-Time SER Characterization of CMOS 65 nm SRAM

We report real-time SER characterization of CMOS 65 nm SRAM memories in both altitude and underground environments. Neutron and alpha-particle SERs are compared with data obtained from accelerated tests and values previously measured for CMOS 130 nm technology.

Real-time Soft-Error testing of 40nm SRAMs

This work reports the real-time Soft-Error Rate (SER) characterization of more than 7 Gbit of SRAM circuits manufactured in 40 nm CMOS technology and subjected to natural radiation (atmospheric neutrons). This experiment has been conducted since March 2011 at mountain altitude (2552 m of elevation) on the ASTEP Platform. The first experimental results, cumulated over more than 7,500 h of operation, are analyzed in terms of single bit upset, multiple cell upsets, physical bitmap and convergence of the SER. The comparison of the experimental data with Monte Carlo simulations and accelerated tests is finally reported and discussed.

Real-time neutron and alpha soft-error rate testing of CMOS 130nm SRAM: Altitude versus underground measurements

This work reports real-time soft-error rate (SER) testing of semiconductor static memories in both altitude and underground environments to separate the component of the SER induced by the cosmic rays (i.e. primarily by atmospheric neutrons) from that caused by on-chip radioactive impurities (alpha-particle emitters). Two European dedicated sites were used to perform long-term real-time measurements with the same setup: the Altitude SEE Test European Platform (ASTEP) at the altitude of 2252 m and the underground laboratory of Modane (LSM, CEA-CNRS) under 1700 m of rock (4800 meters water equivalent). Experimental data obtained using 3.6 Gbit of SRAMs manufactured in CMOS 130 nm technology are reported and analyzed. Comparison with accelerated and simulated SER is also discussed.

Underground Experiment and Modeling of Alpha Emitters Induced Soft-Error Rate in CMOS 65 nm SRAM

This work reports a long-duration

Soft errors induced by natural radiation at ground level in floating gate flash memories

(\sim {3}~{\rm years})

Alpha-Particle Induced Soft-Error Rate in CMOS 130 nm SRAM

real-time underground experiment of 65 nm SRAM technology at the underground laboratory of Modane (LSM) to quantify the impact of alpha-emitter on the Soft-Error Rate (SER). We developed an original and full analytical charge deposition based on non constant Linear Energy Transfer (LET) to accurately model the diffusion/collection approach. Monte Carlo simulation results based on this improved model have been compared to experimental data to analyze the impact of alpha-particle production inside the circuit silicon material for both single and multiple chip upsets. Finally, the respective contributions of alpha emitters and atmospheric neutrons to the circuit Soft-Error Rate (SER) are evaluated and compared, considering additional real-time measurements performed in altitude on the ASTEP platform.

A review of real-time soft-error rate measurements in electronic circuits

This work reports the combined characterization at mountain altitude (on the ASTEP Platform at 2552 m) and at sea-level of more than ~50 Gbit of 90 nm NOR flash memories subjected to natural radiation (atmospheric neutrons). This wafer-level experiment evidences a limited impact of the terrestrial radiation at ground level on the memory SER evaluated without ECC. Experimental values are compared to estimations obtained from Monte Carlo simulation using the TIARA-G4 code combined with a physical model for charge loss in such floating-gate devices.

Combined altitude and underground real-time SER characterization of CMOS technologies on the ASTEP-LSM platform

We report the modeling and simulation of the soft-error rate (SER) in CMOS 130 nm SRAM induced by alpha-particle emission in silicon due to uranium contamination at ppb concentration levels. Monte-Carlo simulation results have been confronted to experimental data obtained from long-duration (>;20 000 h) real-time measurements performed at the under-ground laboratory of Modane (LSM) and from experimental counting characterization using an ultra low background alpha-particle gas proportional counter. The calibration of simulations with the measured SER allowed us to determine a 238U contamination level of 0.37 ppb (considered at secular equilibrium) in very good agreement with both corresponding alpha-particle emissivity levels measured and simulated at wafer-level in the range 1.1 to 2.3 × 10-3 alpha/cm2/h.

Underground characterization and modeling of alpha-particle induced Soft-Error Rate in CMOS 65nm SRAM

The real-time (or life testing) soft-error rate (SER) measurement is an experimental reliability technique to determine the SER from the monitoring of a population of devices subjected to the natural radiation environment and operating under nominal conditions. This review presentation gives a survey over different real-time SER experiments conducted in altitude and/or underground over the past decade. We discuss the specific advantages and limitations of this approach as well as its comparison with accelerated tests using intense particle beams or sources.

Altitude and Underground Real-Time SER Testing of SRAMs Manufactured in CMOS Bulk 130, 65 and 40 nm

This work surveys our 2005–2009 experimental contributions to develop a combined altitude and underground test platform devoted to the soft-error rate (SER) characterization of deca-nanometer CMOS technologies. The platform currently involves two complementary sites to separate the component of the SER induced by the cosmic rays from that caused by on-chip radioactive impurities: the Altitude SEE Test European Platform (ASTEP) located at the altitude of 2252m on the Plateau de Bure (French south Alps) and the Underground Laboratory of Modane (LSM) in the Frejus tunnel under 1700m of rock (4800 meters water equivalent). These two sites have both dedicated instrumentations for neutron monitoring and circuit SER characterization. Long-duration real-time experimental measurements obtained using several gigabits of SRAMs manufactured in CMOS 130 nm and 65 nm technologies are reported and analyzed.