Daniele Leonelli

Fabrication and Analysis of a Heterojunction Line Tunnel FET

This paper presents a new integration scheme to fabricate a Si/Si0.55Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1- μm gate length device shows on current in excess of 20 μA/μm at VGS=VDS=1.2 V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by ~ 0.35 V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration.

Trends and Challenges in Si and Hetero-Junction Tunnel Field Effect Transistors

The stringent requirements imposed by the ITRS not only necessitate the implementation of advanced processing modules but also rely on the introduction of alternative and/or new gate concepts. Multi-gate devices such as FinFETs, showing better scaling performance than single-gate devices due to their better short channel behavior [1], have paved the way to the introduction of Si nanowires. To further enhance the electrical performance one can go a step further and switch over to another operating principle of the devices. Quantum flux and spintronics are examples of possible future devices no longer based on the transport of electrical charges. However, a more direct extension of the present CMOS research is making use of tunnelFETs (TFETs), based on gated P-i-N diodes whereby band-to-band tunneling is used instead of thermo-ionic emission. These devices have a low subthreshold swing (< 60 mV/dec), reduced short-channel effects and enable the fabrication of 3D structures based on vertical nanowires. TFETs can be realized based on a horizontal or vertical technology using either a planar, double gate or MuGFET approach. A benchmarking of some state-ofthe-art TFETs reported in the literature is given in Table 1. This presentation will discuss the different trends and challenges in this field. First some technological issues for both vertical and horizontal devices are addressed. In a second part important aspects related to the device characterization are discussed. Device optimization has to take into account both a large variety of technological parameters such as e.g. implantation profiles, anneal conditions (RTA, spike, laser, SPER etc), gate stack and spacer engineering, and design aspects [3,4]. In the presentation several critical issues will be demonstrated by TFET work on going at IMEC [2-6]. First some technological challenges for both vertical and horizontal devices are addressed. In a second part important aspects related to the device characterization are discussed. Recent results on The performance of a 25 nm wide multi-gate TFETs at a supply voltage of 1.2 V is illustrated in Fig, 1, showing subthreshold swing of 46 mV/dec and an Ion/Ioff ratio of 10. The tunnel efficiency depends on the fin width. Beside static device characteristics one also has to investigate the reliability aspects and the noise performance. The large and indirect Si band gap, however, leads to a low tunneling efficiency limiting the achievable oncurrent. Therefore, research has been triggered toward hetero-structures consisting of a Si drain and intrinsic region and a low band gap material source such as e.g. SiGe, Ge or even an III-V compound. High performing CMOS TFET process flows based on using Ge and GaAs for nand pTFET, respectively, are under investigation. Also trends and challenges for hetero-junction TFETs will be addressed. References [1] A. Vandooren, R. Rooyackers, D. Leonelli, F. Iacopi, E. Kunnen, D. Nguyen, M. Demand, P. Ong, L. Willie, J. Moonens, O. Richard, A.S. Verhulst, W.G. Vandenberghe, G. Groeseneken, S. De Gendt, M.M. Heyns, Proc. 2009 Silicon Nanoelectronics Workshop, p. 21 (2009). [2] D. Leonelli, A. Vandooren, R. Rooyackers, A.S. Verhulst, S. De Gendt, M.M. Heyns and G. Groeseneken, Proc. ESSDERC, p. 170 (2010). [3] D. Leonelli, A. Vandooren, R. Rooyackers, A.S. Verhulst, S. De Gendt, M.M. Heyns and G. Groeseneken, presented at SSDM, Tokyo, Japan (2010). [4] D. Leonelli, A. Vandooren, R. Rooyackers, S. De Gendt, M.M. Heyns and G. Groeseneken, Jpn. J. Appl. Phys., in press. [5] D. Leonelli, A. Vandooren, R. Rooyackers, A.S. Verhulst, S. De Gendt, M.M. Heyns and G. Groeseneken, presented at SSDM, Miyagi, Japan (2009). [6] A.S. Verhulst, W.G. Vandenberghe, D. Leonelli, R. Rooyackers, A. Vandooren, S. De Gendt, M.M. Heyns and G. Groeseneken, Proc. ULSI Process Integration 6, Trans. Electrochem. Soc., vol. 25(7) (2009).

Boosting the On-Current of Si-based Tunnel Field-Effect Transistors

Introduction Promising successors of metal-oxide-semiconductor fieldeffect transistors (MOSFETs) have a sub-60 mV/dec subthreshold swing. The tunnel FET (TFET) is therefore a potential candidate to break through the 1 V supply voltage plateau inhibiting the power scaling of conventional MOSFETs [1-6]. However, due to the injection of carriers into the channel via band-to-band tunneling, design optimization is needed to guarantee sufficient on-current at low voltages for silicon-based TFETs.

Shaping the future of nanoelectronics beyond the Si roadmap with new materials and devices

The use of high mobility channel materials such as Ge and III/V compounds for CMOS applications is being explored. The introduction of these new materials also opens the path towards the introduction of novel device structures which can be used to lower the supply voltage and reduce the power consumption. The results illustrate the possibilities that are created by the combination of new materials and devices to allow scaling of nanoelectronics beyond the Si roadmap.