Anne S. Verhulst

Tunnel field-effect transistor without gate-drain overlap

Tunnel field-effect transistors are promising successors of metal-oxide-semiconductor field-effect transistors because of the absence of short-channel effects and of a subthreshold-slope limit. However, the tunnel devices are ambipolar and, depending on device material properties, they may have low on-currents resulting in low switching speed. The authors have generalized the tunnel field-effect transistor configuration by allowing a shorter gate structure. The proposed device is especially attractive for vertical nanowire-based transistors. As illustrated with device simulations, the authors’ more flexible configuration allows of the reduction of ambipolar behavior, the increase of switching speed, and the decrease of processing complexity.

Direct and Indirect Band-to-Band Tunneling in Germanium-Based TFETs

Germanium is a widely used material for tunnel FETs because of its small band gap and compatibility with silicon. Typically, only the indirect band gap of Ge at 0.66 eV is considered. However, direct band-to-band tunneling (BTBT) in Ge should be included in tunnel FET modeling and simulations since the energy difference between the Ge conduction band edges at the L and Γ valleys is only 0.14 eV at room temperature. In this paper, we theoretically calculate the parameters A and B of Kanes direct and indirect BTBT models at different tunneling directions ([100], [110], and [111]) for Si, Ge and unstrained Si1-xGex. We highlight how the direct BTBT component becomes more important as the Ge mole fraction increases. The calculation of the band-to-band generation rate in the uniform electric field limit reveals that direct tunneling always dominates over indirect tunneling in Ge. The impact of the direct transition in Ge on the performance of two realistic tunnel field-effect transistor configurations is illustrated with TCAD simulations. The influence of field-induced quantum confinement is included in the analysis based on a back-of-the-envelope calculation.

Modeling the single-gate, double-gate, and gate-all-around tunnel field-effect transistor

Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because scaling the supply voltage below 1 V is possible due to the absence of a subthreshold-swing limit of 60 mV/decade. The modeling of the TFET performance, however, is still preliminary. We have developed models allowing a direct comparison between the single-gate, double-gate, and gate-all-around configuration at high drain voltage, when the drain-voltage dependence is negligible, and we provide improved insight in the TFET physics. The dependence of the tunnel current on device parameters is analyzed, in particular, the scaling with gate-dielectric thickness, channel thickness, and dielectric constants of gate dielectric and channel material. We show that scaling the gate-dielectric thickness improves the TFET performance more than scaling the channel thickness and that improvements are often overestimated. There is qualitative agreement between our model and our experimental data.

Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates

As a solution to the low on-current of silicon-based tunnel-FETs (TFETs), the source material of the n-channel TFET is replaced with the small-bandgap material germanium, which results in a current boost up to the same level as the current of MOSFETs. However, no solution has been reported to boost the on-current of the all-silicon p-TFET, a necessity for making an inverter and competing with the MOSFET. We have investigated the heterostructure TFET with respect to complementarity based on our semi-analytical model, and we propose the InxGa1 - xAs-source silicon-TFET as p-TFET. This design is particularly applicable to nanowire-based transistor architectures. We discuss the complementarity of the I-V curves, and we analyze the threshold voltage behavior of the complementary TFETs.

Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization

Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because of the absence of short-channel effects and of a subthreshold-slope limit. As a solution to the low on-currents of silicon-based TFETs, the incorporation of silicon-germanium at the source-channel interface has been considered. However, the understanding of the band-to-band-tunneling mechanism at heterojunctions is incomplete. We have investigated through device simulations and modeling the impact of source-material modifications on the tunnel current in n-channel nanowire TFETs. Our modeling work includes the development of a semi-analytical model, which determines the tunnel probability along the dominant tunnel path in two-dimensional TFETs. In particular, we have analyzed the impact of the bandgap, electron affinity, effective mass, dielectric constant, and density of states of both source and channel material. We show that a small-bandgap source material and a large positive electron-affinity of...

Drain voltage dependent analytical model of tunnel field-effect transistors

Tunnel field-effect transistors (TFETs) are potential successors of metal-oxide-semiconductor FETs because they promise superior input characteristics. However, the output characteristics of TFETs are poorly understood, and sometimes a superlinear onset, undesirable for circuit design, is observed. We present the first analytical model to include the impact of the drain voltage on the TFET performance. The model is developed for both a pure line-tunneling TFET and a pure point-tunneling TFET. Good agreement is observed with device simulations, especially for line-tunneling TFETs. Our model highlights and explains the superlinear onset of the output characteristics, thereby enabling an improved analysis of experimental data. Increasing the source doping level and switching to a smaller bandgap material can remove the undesired onset. We confirm this finding with our experimental data.

Performance Enhancement in Multi Gate Tunneling Field Effect Transistors by Scaling the Fin-Width

This paper discusses the electrical characterization of complementary multiple-gate tunneling field effect transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard complementary metal oxide semiconductor (CMOS) processing, emphasizing the dependence of the tunneling current on the fin-width. A linear dependence of the tunneling current for narrow fins with the square root of the fin width is experimentally reported for the first time. The comparison between narrow fins and planar-like fins offers additional insights about the fin-width dependence. The output characteristic shows a perfect saturation, very attractive for analog circuits. The temperature dependence is measured indicating a weak dependence as expected for tunneling devices. Measured devices with a point slope of 46 mV/dec at low biases and an Ion/Ioff ratio of 106 at a supply voltage of 1.2 V for 25 nm wide fins are reported as best performing devices with a MuGFET technology using a high-k dielectric and a metal gate inserted gate stack.

Analytical model for point and line tunneling in a tunnel field-effect transistor

The tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at nanometer dimensions. In general, the TFET current can be decomposed into two components referred to as point tunneling and line tunneling. In this paper we derive a compact analytical model for the current due to point tunneling complementing the previously derived analytical model for line tunneling. We show that the derived analytical expression for point tunneling provides a more consistent estimate of the TFET current than a commercial device simulator. Both the line and point tunneling current do not show a fixed subthreshold-slope. Three key parameters for design of a TFET are: bandgap, dielectric thickness and source doping level. A small bandgap is beneficial for a high TFET on-current and a low onset voltage. Point tunneling and line tunneling show a strong dependance on gate dielectric thickness and doping concentration respectively.

Analytical model for a tunnel field-effect transistor

The tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at nanometer dimensions. Due to the absence of a simple analytical model for the TFET, the working principle is generally not well understood. In this paper a new TFET structure is introduced and using Kanepsilas model, an analytical expression for the current through the TFET is derived. Furthermore, a compact expression for the TFET current is derived and conclusions concerning TFET design are drawn. The obtained analytical expressions are compared with results from a 2D device simulator and good agreement at low gate voltages is demonstrated.

Figure of merit for and identification of sub-60 mV/decade devices

A figure of merit I60 is proposed for sub-60 mV/decade devices as the highest current where the input characteristics exhibit a transition from sub- to super-60 mV/decade behavior. For sub-60 mV/decade devices to be competitive with metal-oxide-semiconductor field-effect devices, I60 has to be in the 1-10 μA/μm range. The best experimental tunnel field-effect transistors (TFETs) in the literature only have an I60 of 6×10−3 μA/μm but using theoretical simulations, we show that an I60 of up to 10 μA/μm should be attainable. It is proven that the Schottky barrier FET (SBFET) has a 60 mV/decade subthreshold swing limit while combining a SBFET and a TFET does improve performance.