Danielle Vanhaeren

Heavy ion implantation in Ge: Dramatic radiation induced morphology in Ge

High dose ion implantation of heavy elements in Ge induces a rough surface and profile distortions when measured with secondary ion mass spectrometry. In the case of Sb large subsurface holes are also induced by the implantation. The formation of these subsurface structures starts abruptly at a dose between 5∙1014 and 1015at∕cm2. The addition of a SiO2 capping layer on top of Ge prevents the formation of the surface roughness, but has limited impact on the void formation. These voids originate from vacancy clustering during the implant process. Anneal studies show that it is impossible to remove these structures by annealing, limiting the usefulness of high dose Sb implants in Ge for junction formation. In the case of As implantation a similar surface roughness is seen but no void formation. Adding a cap layer removes the surface roughness in this case and improves the secondary ion mass spectroscopy profiles.

Enhanced Performance of PMOS MUGFET via Integration of Conformal Plasma-Doped Source/Drain Extensions

For the first time, scaled PMOS MUGFET devices with TiCN/HfO2 gate stack is doped with specific pulsed plasma doping processes. This paper first highlights the key benefit brought by conformal source/drain extensions, demonstrates how pulsed plasma doping process can be tuned to conformal dope very dense fin structures and finally shows that high performance (+24% vs. ion implant reference) multi-gate pMOS device (720 muA/mum @ Ioff 20nA/mum, at Vds = -1.2V) is achieved with extensions formed by optimized PLAD process

Active dopant characterization methodology for germanium

In order to reach the ITRS goals for future complementary metal-oxide semiconductor technologies there is a growing interest in using germanium as an alternative substrate material in view of its higher mobility. Different species and thermal budgets are presently being investigated in order to determine the most likely candidates for the required junction formation. A key issue is the accurate determination of the achievable electrical activation, i.e., the reliable measurement of the sheet resistance and electrical depth profile. In order to be applicable to Ge-based junctions, standard techniques such as the spreading resistance probe and scanning spreading resistance microscopy (SSRM) need to be reevaluated in terms of their performance and operational conditions. First, the significantly different behavior of germanium calibration curves (versus silicon) will be discussed. Next, the shape and characteristics of the probe imprints (Ge is softer than Si) and the differences in raw data behavior will be...

Impact of probe penetration on the electrical characterization of sub-50 nm profiles

The spreading resistance probe (SRP) and four point probe (FPP) use, respectively, two or four metal probes with loads in the range of 5–100 g to obtain indispensable information on the electrical characteristics (sheet resistance, junction depth, activation degree, profile shape) of impurity depth profiles in silicon. Recently, however, it has been reported that FPP sheet values are becoming irreproducible and that SRP depth profiles can be significantly shallower than the corresponding secondary ion mass spectrometry dopant profiles for ultrashallow structures. In this work we analyze the impact of probe penetration on the accuracy of SRP and FPP measurements for a series of sub-50 nm profiles with different steepness and substrate level. The probe penetration has been measured by atomic force microscopy and ranged from 5 to 130 nm. The FPP sheet resistance errors of up to 300%, as found for the higher loads, can be correlated with the penetration of the probes through the electrical junction taking int...

Bulk Properties of MOCVD-Deposited HfO2 Layers for High k Dielectric Applications

The physical bulk properties of metalorganic chemical vapor deposited (MOCVD) deposited HfO 2 layers were characterized as a function of deposition temperature. thickness, and starting surface. It is shown that depositing HfO 2 layers at 300°C results in a lower density film compared to films deposited at higher temperature (e.g., 485 and 600°C). In addition, it is shown that layers deposited at 300°C contain significant amounts of carbon originating from the organic precursor (tetrakis-diethylamidohafnium). As a result of the low density and/or carbon contamination, the dielectric properties of these layers are very poor. It is observed that the density of the film is heavily dependent on the thickness, where very thin layers have a density that is only a fraction of the bulk density regardless of the deposition temperature. For thicker layers, a higher deposition temperature is seen to result in a higher density, although still lower than bulk density, as observed by ellipsometric porosimetry. Finally, the crystalline state of the material is found to be dependent on the deposition temperature, thickness, and post-deposition anneal. Based on our results, MOCVD deposited HfO 2 layers are expected to be polycrystalline and present in its cubic and/or monoclinic phase.

2D-TCAD Process Calibration for a High Speed QSA SiGe:C HBT Verified with SSRM

In this work, we present the use of SSRM, an electrical characterization technique based on atomic resistance microscopy (AFM), as a verification tool for the accurate calibration of two dimensional (2D) process simulations on advanced high speed bipolar HBT devices with fT/fmax values exceeding 200GHz. The 2D HBT process simulator has been calibrated based on SIMS measurements and TEM pictures. The process simulations consider coupled diffusion of carbon and silicon point defects under several RTA conditions [1]. Kick-Out and Frank-Turnbull mechanisms model the carbon diffusion. Extended short-loop experiments under equilibrium and non-equilibrium conditions increased the accuracy of the simulations [2]. Lateral and vertical scaling of the bipolar device dimensions is an absolute requirement for obtaining current and power cutoff frequencies (fT, fmax) above 200GHz [3]. The state-of-the-art QSA HBT investigated in this work for instance has an enclosure of active area over the poly emitter of only 0.03μm. As the external base implantation, needed to obtain low base resistance, is done after the poly emitter patterning, a precise determination of the base collector junction becomes difficult but at the same time important, taking into account the interaction with the selectively implanted collector (SIC) and the importance of the base-collector junction location for the DC device characteristics. Simulations using the calibrated 2D-TCAD platform show the different shapes of the external base-collector metallurgical junction as a function of the poly emitter sidewall angle (fig 1). The vertical depth of the basecollector metallurgical junction along the STI drops from 90nm to 75nm and even 45nm for a poly emitter sidewall angle of respectively 90°, 80° and 73°. From crosssectional pictures we know that the poly emitter sidewall angle is around 80°, but so far we were unable to verify the exact position of the base-collector metallurgical junction on real silicon. A key advantage of the SSRM technique however is its capability to determine the precise location of electrical transistor junctions. The improvements in sample preparation and the introduction of full diamond probes have enabled a drastic increase of the spatial resolution down to 1-3nm [4,5], even for HBT transistors where many materials with different hardness are present (silicon, polysilicon, oxide, nitride, silicide, SiGe). Figures 2 and 3 show such SSRM plots for the QSA 0.13μm SiGe:C HBT. A comparison is shown with a 2DTCAD plot and with a TEM picture respectively. Geometrical distances and the base-collector junction can be clearly distinguished on the SSRM plots. A quantification of the key geometrical and electrical distances extracted from the SSRM data are summarized in table 1. They are compared with the TCAD values. SSRM quantifies correctly known geometrical values like for instance the nitride thickness of the emitter window and the oxide undercut under this nitride. The measured lateral and vertical electrical junction depths from SSRM correspond well with the values extracted from the calibrated 2D-TCAD platform. We conclude therefore that the 2D-TCAD process simulator is correctly calibrated. This TCAD platform will be used for future process optimization of advanced high speed HBT devices.

Using scaling laws to understand the growth mechanism of atomic layer deposited WNxCy films on methyl-terminated surfaces

Atomic layer deposition (ALD) of tungsten nitride carbide (WNxCy) on methyl-terminated self-assembled monolayers (SAMs) is investigated. SAM substrates provide extended transient regimes of different lengths, during which the WNxCy film growth is nonlinear. The extent of this offset from linear growth depends on the alkyl chain length. The film morphology is characterized by atomic force microscopy, which reveals island growth and fractal behavior. During the transient regime, WNxCy deposition shows nonconservative growth, as revealed by the low film density and a roughness exponent α of ∼0.4–0.5. During the linear growth regime, a conservative mechanism is observed, characterized by a higher, constant film density and α∼0.7. These observations do not apply to all ALD deposited films. In particular, ALD HfO2 films follow a conservative-type mechanism during the entire range of growth.

Characterization of porous structure in ultra-low- K dielectrics by depositing thin conductive cap layers

A new methodology to characterize the porous structure of mesoporous dielectrics is presented. The technique is based on the evaluation of the degree of continuity of thin Ta(N) cap layers deposited by physical vapour deposition on top of blanket dielectric films, various ultra-low-k films prepared by completely different techniques have been investigated, showing that a clear dependence can be established between the increase in sheet resistance of the conductive cap layer and the amount of open pores at the surface of the dielectric films.

Interplay Between Statistical Variability and Reliability in Contemporary pMOSFETs: Measurements Versus Simulations

This paper presents an extensive study of the interplay between as-fabricated (time-zero) variability and gate oxide reliability (time-dependent variability) in contemporary pMOSFETs. We compare physical simulation results using the atomistic simulator GARAND with experimental measurements. The TCAD simulations are accurately calibrated to reproduce the average transistor behavior. When random discrete dopants, line edge roughness, and gate polysilicon granularity are considered, the simulations accurately reproduce time-zero (as-fabricated) statistical variability, as well as time-dependent variability data, represented by threshold voltage shift distributions. The calibrated simulations are then used to predict the reliability behavior at different bias conditions and for different device dimensions.

Reliability aware simulation flow: From TCAD calibration to circuit level analysis

In this paper, we present a simulation flow based on TCAD model calibration against experimental transistor measurement and doping profile reverse engineering. Further the physical astatistical variability simulations at TCAD level are also adjusted to match the statistical measurement. This is folloed up by oxide wear out reliability characterization and modelling. Finally statistical compact model libraries for fresh and aged devices are extracted from large samples of TCAD simulation results allowing the performance analysis of a 6T SRAM cell. The calibration procedure has been performed on P and NMOS transistors fabricated and characterized by IMEC, while Glasgow University performed the TCAD reverse engineering and calibration, and the statistical simulations using dedicated Gold Standard Simulations tools.