Ning-Yi Wang

A 60GHz CMOS VCO Using On-Chip Resonator with Embedded Artificial Dielectric for Size, Loss and Noise Reduction

An on-chip resonator with artificial dielectric in place of the LC tank yields reduced metal/substrate losses, higher resonator Q and alambda/4 length reduction of 4.7 times. The VCO uses 90nm CMOS, with 0.015mm2 area, consumes 1.9mW and has a measured phase noise of -100dBc/Hz at 1MHz offset. The FOM is -193dBc/Hz

A 60GHz CMOS Differential Receiver Front-End Using On-Chip Transformer for 1.2 Volt Operation with Enhanced Gain and Linearity

A compact 60GHz CMOS differential direct conversion receiver front-end based on eight-metal-layer interleaved on-chip transformers is realized for low voltage (1.2V) and high gain (24dB) operation with input 1dB compression point of -11dBm, noise figure of 10.5 dB and power consumption of 4.3mW/arm. Compared with prior arts in CMOS, this receiver achieves the highest gain without an output buffer, highest linearity, lowest noise, and lowest power consumption with smallest die area of 0.022mm2

A V-band self-healing power amplifier with adaptive feedback bias control in 65 nm CMOS

A self-healing two-stage 60 GHz power amplifier (PA) with amplitude/phase compensation is realized in 65 nm CMOS. An adaptive feedback bias scheme with three control knobs is proposed to extend the linear operating region and enhance chip-to-chip performance yield; allowing a 5.5 dB improvement of the output 1-dB compression point (P1dB) and a less than 2% chip-to-chip gain variation. At a 1 V supply, the fully differential PA achieves a saturation output power (Psat) of 14.85 dBm with a peak power-added-efficiency (PAE) of 16.2%. With the on-chip amplitude compensation, the P1dB is extended to 13.7 dBm. With the on-chip phase compensation, the output phase variation is minimized to less than 0.5 degree. To the best of our knowledge, this PA provides the highest Psat and P1dB with simultaneous high PAE for a single PA reported to date. The PA delivers a linear gain of 9.7 dB and has a 7 GHz bandwidth from 55.5 to 62.5 GHz with a very compact area of 0.042 mm2.

A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chip

The available ISM band from 57-65GHz has become attractive for high-speed wireless applications including mass data transfer, streaming high-definition video and even biomedical applications. While silicon based data transceivers at mm-wave frequencies have become increasingly mature in recent years [1,2,3], the primary focus of the circuit community remains on the design of mm-wave front-ends to achieve higher data rates through higher-order modulation and beamforming techniques. However, the sustainability of such mm-wave systems when integrated in a SoC has not been addressed in the context of die performance yield and device aging. This problem is especially challenging for the implementation of mm-wave SoCs in deep sub-micron technology due to its process & operating temperature variations and limited ft / fmax with respect to the operation frequency.

A 60 GHz Tunable Output Profile Power Amplifier in 65 nm CMOS

A fully integrated three-stage 60 GHz power amplifier with amplitude/phase compensation is realized in 65 nm CMOS. An adaptive feedback bias scheme with three control knobs is proposed to extend the linear operating region. At a supply voltage of 1 V, the fully differential amplifier achieves a linear gain of 15 dB and occupies a compact area of 0.056 mm2. It achieves a minimal Psat-P1dB separation of 0.6 dB by extending the P1dB by 8.5 dB. To our best knowledge, this is the smallest Psat-P1dB separation reported to date. With on-chip phase compensation, the output phase variation is reduced by 57%.

A Blocker-Tolerant Current Mode 60-GHz Receiver With 7.5-GHz Bandwidth and 3.8-dB Minimum NF in 65-nm CMOS

A current-mode 60-GHz direct-conversion receiver, which can break performance tradeoffs among bandwidth, noise figure (NF), and linearity is designed and realized in 65-nm CMOS. The 60-GHz receiver employs the novel frequency-staggered series resonance common source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receivers current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature local oscillator generations, the fabricated receiver simultaneously achieves minimal NF of 3.8 dB, RF bandwidth of 7.5 GHz, output P1 dB of 1 dBm, and maximum conversion gain of 36 dB. The receiver is capable of tolerating out-of-channel blocker up to -9 dBm at 3.5 GHz away. It occupies a silicon area of 1.3 mm2 and draws 25.5 mA of current from a 1-V supply.

A Current-Mode mm-Wave direct-conversion receiver with 7.5GHz Bandwidth, 3.8dB minimum noise-figure and +1dBm P 1dB, out linearity for high data rate communications

A current-mode mm-wave direct-conversion receiver breaking trade-offs among bandwidth, NF and linearity is designed and realized in 65nm CMOS. The 60GHz receiver employs novel Frequency-staggered Series Resonance Common Source (FSRCS) stage to extend RF bandwidth with superior noise performance. The receivers current-mode operation offers excellent out-of-band blocker tolerance and linearity. With on-chip quadrature LO generations, the fabricated receiver simultaneously achieves minimal noise figure of 3.8dB, RF bandwidth of 7.5GHz, output P1dB of 1dBm, maximum conversion gain of 32dB, and IRR of -35dB. The receiver is capable of tolerating outof-channel blocker up to -9dBm at 3.5GHz away. It occupies silicon area of 1.3mm2 and draws 25.5mA from 1V supply.

A Compact and Low Power 5–10 GHz Quadrature Local Oscillator for Cognitive Radio Applications

This paper presents the design and implementation of a compact and low power quadrature local oscillator (LO) for creating 13.3-20 GHz signal initially from a differentially tuned LC-VCO and then converting it to the desired 5-10 GHz with continuous frequency coverage. To accomplish such purpose, a 4-stage differential injection-locked ring oscillator (ILRO) is used subsequently to the latch-based divider to generate quadrature output phases without restricting 50% duty cycle from input signals as those of conventional divide-by-2 approaches. When implemented in a 65 nm general purpose CMOS IC technology, the integrated quadrature-phased LO consumes 22 mA of current at a 1 V supply and is able to exhibit the worst-case phase noise of -104 dBc/Hz at 1 MHz offset across the entire 5-10 GHz band for intended cognitive radio applications.

A 60dB gain and 4dB noise figure CMOS V-band receiver based on two-dimensional passive G m -enhancement

A direct conversion receiver which consists of low noise amplifier (LNA), mixer and programmable gain amplifier (PGA) for V-band (60GHz) applications is designed and realized in 65nm CMOS. A novel two-dimensional passive gm-enhancement technique is devised to boost the conversion gain and lower the Noise Figure (NF) with insignificant power overhead. An overall minimum SSB NF of 3.9dB and a maximum power conversion gain of 60dB have been validated from such fabricated receiver that occupies core silicon area of 0.2mm2 and draws 34mA from 1V supply.

A single-LC-tank 5–10 GHz quadrature local oscillator for cognitive radio applications

This paper presents a local oscillator (LO) that converts oscillation frequencies of 13.3–20GHz from a single-LC-tank VCO to the intended 5–10GHz with continuous frequency coverage. A 4-stage differential injection-locked ring oscillator (ILRO) is used after the latch-based divider to produce quadrature output phases without requiring 50% duty cycle of input signals as those of conventional divide-by-2 approaches. When implemented in 65nm CMOS, the prototype LO consumes 22mA at 1V supply and is able to exhibit a worst-case phase noise of −102dBc/Hz at 1MHz offset across the entire 5–10GHz band for projected cognitive radio applications.