Dariusz Polok

Popular microcontrollers execute IEC 61131-3 standard operators and functional blocks in simply automatic control tasks

Over the recent decades a common approach seems to be taken for granted that only dedicated Central Processing Unit (CPU) offered as self-contained modules by various manufacturers are the only solution for implementation of Programmable Logic Controllers (PLC). To demonstrate right the contrary authors of this study reveal various CPU solutions of PLCs developed on the basis of some typical microcontrollers, including the ones from the families MCS-51, AVR and ARM with the Cortex M3 core. These CPUs were then employed to run a control program developed in an Instruction List (IL) language that meets recommendations of the IEC-61131-3 standard. The paper demonstrates that the basic operators of the IL language can be used to simplify bodies of the standard defined function and function blocks. The rules are outlined that the authors adhered to at development of commands for the IL language with dedicated examples that explain how these commands can be used to define functionalities for operational modules of counters and timers and a combinational Boolean function - on the example of the LIMIT procedure. It is also suggested to define several new operators that additionally simplify the notation. The scope of investigations includes also comparison between the solutions suggested by stipulations of the standard in question and the own solutions proposed by the authors with presentation of the outcome from the comparison. The disclosed considerations served as the basis to suggest the new architecture for a CPU that is suitable for operation in line with rules imposed by the standard, but on the other hand it can be used for operation with some modifications suggested by the authors and intended to reduce processing time for some operators, Boolean functions and functional blocks.

About Implementation of IEC 61131-3 IL Operators in Standard Microcontrollers

Abstract The paper presents various solutions for a Central Processing Unit (CPU) of Programmable Logic Controllers (PLC) developed on the basis of three typical microcontrollers from the families MCS- 51, AVR and ARM with the Cortex M3 core. The control program for these CPUs was developed in an Instruction List (IL) language that was in conformity with recommendations of the IEC-61131-3 standard. The most important issue that had to be resolved was translation of original commands in the IL language into own programming languages of the mentioned microcontrollers. The paper demonstrates that the commands of the IL language can be translated into fragments of runtime programs via procedures developed in the C language. The results achieved from all competed experiments make it possible to conclude that it is possible to design an efficient CPU, competitive in terms of the speed and time of the program execution, with use of standard microcontrollers.

FPGA-based two-processor CPU for PLC

The paper reveals a two-processor Central Processing Unit (CPU) designed for Programmable Logic Controllers (PLC). The CPU is made up of a 1-bit (bit-type) processor and a 32-bit (word-type) processor. The both processors are operated totally independently from one another and information between them is exchanged via a exchange memory module. The 1-bit processor collaborates with edge detectors whilst the 32-bit processor is dedicated for implementation of timers and counters as well as enables execution of arithmetic operations on 32-bit integers and floating point variables. The both processors have been developed as specialized structures capable of executing control routines developed in the Instruction List (IL) programming language in line with requirements of the EN 61131-3 standard. The study presents a new approach to development of the exchange memory module and edge detectors as well as implementation of timers and counters. It is the approach that combines both software and hardware solutions, which makes them more efficient in terms of time performance as compared to already known solutions. Finally the CPU was designed with use of the hardware description language and then implemented in FPGA resources. This paper discloses results of the synthesis and execution times achieved for both individual instructions and benchmarks routines running on the newly designed CPU. The accomplished results make it possible to conclude that the CPU can be considered as an alternative solution to other units available from the market whilst the capability to execute algorithms developed in strict conformity to EN 61131-3 standard is its advantage.

About some peculiar approaches to seeking the Ashenhurst decomposition of logic functions in the Reed-Muller spectrum domain

The paper deals with the problem of logic function decomposition in Reed-Muller spectrum. A logic function decomposition in this domain was interesting because for n variables of a logic function as many as two power n polarizations of Reed-Muller spectrums of the logic function exist and the space where decomposition of such a function can be sought for is extremely large. In the paper there was check if searching for decomposition with spectrum of other polarization then polarization zero leads to a success. Moreover the authors of the paper have observed that it was possible to find a decomposition for some logic functions by making permutations between the functions variables. The paper presents few examples that prove the idea. These findings even more expand the space for seeking for the decomposition.

Performance analysis of a PMSM drive with torque and speed control

The paper presents performance analysis of a permanent magnet synchronous motor (PMSM) drive with torque and speed control. The PMSM motor requires sinusoidal stator currents to produce constant torque. The paper presents constituents for the mathematical analysis of the motor operation within the dq-axis model. The mathematical model serves as inspiration for development of a drive design based on the DSP processor and IGBT power module. The measurement system consists of a control unit equipped with an inverter and an encoder, the PMSM drive (500W; 5Nm; 800 rpm), a torque measuring device and a motor that work in the generator mode. The performance analysis has been performed in two control intervals. It is possible to operate the PMSM with the speed that exceeds the rated rpm if the permanent-magnet excitation is weakened by a demagnetising field component produced by the stator winding. However, it leads to a decrease of the motor efficiency. The conducted experiments have shown, that in the second control interval it is possible to increase the motor speed by about 30% as compared to the nominal rpm (overspeed).

Seeking for decomposition of a Boolean function in the reed-müller spectral domain by Means of permutation between function variables

The paper deals with the problem of logic function decomposition in Reed-Muller spectrum. A Boolean function decomposition in this domain is interesting because for n variables of a Boolean function as many as two power n Reed-Muller expansions of the Boolean function exist and the space where decomposition of such a function can be sought for is extremely large. The authors of the paper have observed that it was possible to find a decomposition for some Boolean functions by making permutations between the functions variables. The paper presents few examples that prove the idea. These findings expand the space for seeking for the optimum decomposition even more.

Programmable Logic Controller based on reconfigurable logic

The paper presents an idea of a Programmable Logic Controller for binary control implemented in an FPGA device with use of custom designed implementation tools. It is an extension of previously proposed architecture that is mainly limited by hardwired connection. Based on connection resources available in FPGA the new architecture is proposed. Possible computation capabilities of FPGA devices are discussed. The research task is continued and looking for nonmultiplexed solution with extended usage of programmable connections and better exploit of logic resources.

Analysis of implementation opportunities for selected conventional counter-based circuits in selected FPGA structures in terms of time performance

Among many parameters that are crucial for performance of FPGA (Field Programmable Gate Arrays) structures the high operation speed combined with reasonable and cost-efficient layout seems to be the most important feature. In pace with evolution of FPGA structures a common belief has spread out that each subsequent FPGA structure, originated from the same family, is better than its predecessor in terms of quality, efficiency and operation speed of circuits implemented within such a structure. However, authors of this study, being forced to simultaneously use both less and more recent structures have come to the conclusion that such a belief is not obvious and need not be true under all circumstances. It is why they decided to verify their expectations on the basis of experiments associated with implementation of a certain digital circuit family, preferably very popular and in common use. Thus, the experiments were focused on conventional counter structures, both synchronous and asynchronous, that were implemented within the FPGA structures from XILINX. This study is intended to demonstrate that employment of the most recent FPGA structures for implementation of typical digital circuits (in particular counters and the like) is not always the most beneficial solution leading to the desired effects. It is recommended to compare the final outcome from implementation of the same circuit in FPGA structures from various families, including less recent ones that may prove more beneficial, not only by virtue of the logic structure but also the commercial properties.

Application of embedded systems based on single-board computers on an example of the DIMM PC

The paper deals with a number of problems related to implementation of embedded systems that use single-board computers. These considerations are carried out on a specific model of such a computer, namely DIMM-PC. Actually, this computer is a power-saving and a comprehensive implementation of a typical PC computer, equipped with a ‘hard disk’ emulated on FLASH memory units and assembled on a PCB with extremely small dimensions. In spite of small dimensions, its processing capacities are pretty large, which makes the system useful for implementation of embedded systems, perfectly suitable for field control with communication via RS232/485, or Ethernet distributed networks.

Analysis of Timings in Networks That Use TCP/IP or UDP/IP Protocols for Communication with Industrial Controllers in Mechatronic Systems

In pace with the technical progress in controllability of mechatronic systems including machines and industrial equipment, the systems of industrial controllers (both PLC and microprocessor ones) more and more frequently use Ethernet-based networks for communication with supervising centres and surveillance systems. The Internet offers unsurpassed opportunities of remote programming as well as remote development, debugging and tuning the existing control software. Nowadays, supporting the remote tools and facilities is the essential requirement that is mandatory when decisions on purchase and implementation of industrial controllers are made. It is the underlying reason to launch more extensive research in that field. The presented paper describes dedicated software that has been developed to enable communication over the Internet within dispersed control systems. The system makes it possible to transmit and to receive short messages to and from the controlled actuators as well as to perform basic tasks related to management of data flow in networks that use TCD and UDP protocols. The special attention was paid to dynamic phenomena of the data exchange process. It is an issue of crucial importance within dispersed systems of industrial controllers and it assures efficient operation of the entire system owing to timely and quick respond to fast-changing control signals. Data exchange was carried out with the use of so-called primitives for Berkeley sockets that serve as primary structures within the network and are capable to perform basic operation such as creation and destruction, assigning network addresses to the sockets, establishing connections, transmission (broadcasting), receiving, etc. To measure time intervals of communication sessions the authors took advantage of functional features of contemporary motherboards of PC computers. In particular, the function of the API counter was used as it allows to readout the fast internal 64-bit counter which, in consequence, enabled measurement of time gaps with accuracy up to single microseconds. The described software performs tests of communication facilities in terms of their applicability to fast data exchange between field control modules of the control system and the CPU, whereas the entire communication is performed via Internet. Therefore the reaction time of a hypothetical field controller in respond to switchovers of the input signals or interrupt events can be measured. The communication and measurements were performed over local and national internet networks as well as for GPRS networks. Measurement results are presented in a compact form of tables that is suitable for further analysis. The presented system is able to transmit diagnostic information therefore it can be also used for integrated diagnostics of mechatronic systems as well as for location and analysis of possible failures within the in-field systems.