Robert Czerwinski

Area and speed oriented synthesis of FSMs for PAL-based CPLDs

New two-step methods of FSMs synthesis for PAL-based CPLDs are presented in the paper. The methods strive to find the optimum fit for a FSM to the structure of CPLD and aim at area and speed optimization. The first step for both methods is original state assignment that includes: techniques of two-level minimization, the limited number of terms contained in the cell and elements of adjusting to the logic optimization. The second step in the method oriented toward area minimization is PAL-oriented multi-level optimization, which is a search for implicants that can be shared by several functions. The second step in the method oriented toward speed maximization is based on utilizing tri-state buffers, thus enabling achievement of a one-logic-level output block.

State assignment for PAL-based CPLDs

In the paper, the state assignment methods of the finite state machines for PAL-based structures are presented. A main feature of the PAL-cell is a limited number of product terms (k-AND-gates) that are connected to a single sum (OR-gate). Function, which is the sum of p-implicants, when p/spl ne/k, does not take full advantage of the cell. When p>k, implementation is multi-cell (so multi-level). The main idea of solving this problem is to count the number of product terms during the process of state assignment. First algorithm leads to automata which take advantage of the number of PAL-cell terms. Second approach is dedicated to state assignment of fast automata. Methods based on primary and secondary merging conditions are presented. In one of the most basic states of the logic synthesis of sequential devices, the elements referring to restrictions of PAL-based CPLDs are taken into account.

Synthesis of finite state machines for CPLDs

Synthesis of finite state machines for CPLDs The paper presents a new two-step approach to FSM synthesis for PAL-based CPLDs that strives to find an optimum fit of an FSM to the structure of the CPLD. The first step, the original state assignment method, includes techniques of two-level minimization and aims at area minimization. The second step, PAL-oriented multi-level optimization, is a search for implicants that can be shared by several functions. It is based on the graph of outputs. Results of experiments prove that the presented approach is especially effective for PAL-based CPLD structures containing a low number of product terms.

An IEC 61131-3-based PLC implemented by means of an FPGA

The paper discusses the design process of a programmable logic controller implemented by means of an FPGA device. The PLC implements on the machine language level a subset of the instruction set defined in the EN 61131-3 norm. Different aspects of instruction list and hardware architecture design are presented, however two aspects are the most important: Central Processing Unit (CPU) and the Arithmetic and Logic Unit (ALU). The ALU can execute 34 operations, which include the basic logic operations, comparators, and the four basic arithmetic operations. The operations can be performed for fixed-point and floating-point numbers. All the operations are implemented fully in hardware, so the solution is fast. The developed PLC is implemented using an FPGA device; however, the HDL models used for synthesis can be easily ported to an ASIC.

Synthesis of FSMs

An introduction to state assignment is presented in the chapter. Elements of two-level minimization must be included in the state assignment in order to adjust the number of implicants to the number of product terms contained in the cell. Primary and secondary merging conditions are introduced. The implicants distribution table is defined to distribute the implicants among single functions.

FPGA Implementation of Programmable Logic Controller Compliant with EN 61131-3

Abstract The paper discusses the design process of a simple programmable logic controller. The conception of the PLC is presented. The idea is to develop PLC, which is compatible with EN 61131-3 standard. This part of standard refers to programming languages. However, instructions of the PLC are directly related to the hardware structure of the PLC. The most important part of the PLC is central processing unit and the paper especially focuses on this aspect. Instruction set, encoding and some elements of the design are presented and the paper is structured to show design flow from instruction list to a hardware design. The CPU was implemented in FPGA device.

State Machine description oriented towards effective usage of vendor-independent synthesis tools

Abstract The paper concerns the problem of Finite State Machine (FSM) description in Hardware Description Languages (HDL), and effective usage of vendor-independent synthesis tools, including academic software, in synthesis dedicated for Complex Programmable Logic Devices (CPLD-s). The authors propose an alternative method of porting a design from a vendor-independent synthesis tool to a vendor system, for completing the implementation stage. The method utilises a special style of VHDL modelling, so the description is universal and comprehendible to a human. Efficiency of the method was verified by experiments carried out using academic software, and leading commercial tools.

State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers

The logic synthesis of ultra-high-speed FSMs is presented. The state assignment is based on a well-known method that uses output vectors. This technique is adjusted to include elements of two-level minimization and takes into account the limited number of terms contained in the programmable-AND/fixed-OR logic cell. The state assignment is based on a special form of the binary decision tree. The second phase of the FSM design is logic optimization. The optimization method is based on tristate buffers, thus making possible a one-logic-level FSM structure. The key point is to search partition variables that control the tristate buffers. This technique can also be applied to combinational circuits or the output block of FSMs only. Algorithms for state assignment and optimization are presented and richly illustrated by examples. The method is dedicated to using specific features of complex programmable logic devices. Experimental results prove its effectiveness (e.g., the implementation of the the 16-bit counter requires 136 logic cells and one-logic-cell level instead of 213 cells and four levels). The optimization method using tristate buffers and a state assignment binary decision tree can be directly applied to FPGA-dedicated logic synthesis.

Performance analysis of a PMSM drive with torque and speed control

The paper presents performance analysis of a permanent magnet synchronous motor (PMSM) drive with torque and speed control. The PMSM motor requires sinusoidal stator currents to produce constant torque. The paper presents constituents for the mathematical analysis of the motor operation within the dq-axis model. The mathematical model serves as inspiration for development of a drive design based on the DSP processor and IGBT power module. The measurement system consists of a control unit equipped with an inverter and an encoder, the PMSM drive (500W; 5Nm; 800 rpm), a torque measuring device and a motor that work in the generator mode. The performance analysis has been performed in two control intervals. It is possible to operate the PMSM with the speed that exceeds the rated rpm if the permanent-magnet excitation is weakened by a demagnetising field component produced by the stator winding. However, it leads to a decrease of the motor efficiency. The conducted experiments have shown, that in the second control interval it is possible to increase the motor speed by about 30% as compared to the nominal rpm (overspeed).

CPLD-oriented Synthesis of Finite State Machines

The purpose of the paper is to present a new approach to FSM synthesis for PAL-based CPLDs. The proposed approach consists of the original method of the state assignment and PAL-oriented multi-level optimization. The aim of the proposed state assignment method is to minimize the number of the PAL-based macrocells by fitting the FSM to the structure of the CPLD as good as possible. The essence of PAL-oriented multi-level optimization is to search for multi-output implicants that can be shared by several functions. Results of experiments prove that the proposed algorithm leads to significant reduction of chip area in relation to the previously published methods and vendor-tools.