Miroslaw Chmiel

Remarks on Parallel Bit-Byte CPU Structures of the Programmable Logic Controller

The paper presents some hardware solutions for the bit-byte CPU of a PLC, which are oriented for maximum optimisation of data exchange between the CPU processors. The optimization intends maximum utilization of the possibilities given by the two-processor architecture of the CPUs. The key point is preserving high speed of instruction processing by the bit-processor, and high functionality of the byte-processor. The optimal structure should enable the processors to work in parallel as much as possible, and minimize the situation, when one processor has to wait for the other.

Central Processing Units for PLC implementation in Virtex-4 FPGA

Abstract The paper presents an approach to the design and construction of central processing units for programmable logic controllers implemented in a FPGA development platform. Presented units are optimised for minimum response- and throughput time. The CPU structure is based on bit-word architecture and two types of control data exchange methods: with handshaking – control data are passed through the two flip-flop units with acknowledgement; without handshaking – control data are passed through the dual port RAM. Third unit – simple one processor – built to compare with the above two. The paper presents specific timers/counters hardware construction solution. Additionally it presents implementation results which show how many FPGA circuit resources are used to implement presented units.

An IEC 61131-3-based PLC implemented by means of an FPGA

The paper discusses the design process of a programmable logic controller implemented by means of an FPGA device. The PLC implements on the machine language level a subset of the instruction set defined in the EN 61131-3 norm. Different aspects of instruction list and hardware architecture design are presented, however two aspects are the most important: Central Processing Unit (CPU) and the Arithmetic and Logic Unit (ALU). The ALU can execute 34 operations, which include the basic logic operations, comparators, and the four basic arithmetic operations. The operations can be performed for fixed-point and floating-point numbers. All the operations are implemented fully in hardware, so the solution is fast. The developed PLC is implemented using an FPGA device; however, the HDL models used for synthesis can be easily ported to an ASIC.

A FPGA-Based Bit-Word PLC CPUs Development Platform

Abstract The conception of the hardware-software platform is presented in the paper. Presented platform is designed in order to test different constructions of the central processing units dedicated to programmable logic controllers. Selected hardware solutions for the PLC dual processor bit-byte (word) CPUs, which are oriented for optimised maximum utilization of capabilities of the two-processor architecture of the CPU are presented in the paper. The key point is preserving high speed of instruction processing by the bit-processor, and high speed and functionality of the byte (word)-processor. The structure should enable the processors to work in concurrent mode as far as it is possible, and minimize the situations, when one processor has to wait for the other. Designed platform is based on the development board equipped with Xilinx Virtex-4 FPGA. Software tool for testing possibilities of the selected units and testing utilization of the programmable structure was also developed.

An Idea of Event-Driven Program Tasks Execution

Abstract The paper presents modified idea of program execution in PLCs. Instead of serial cyclic execution of control program event-driven execution is proposed. Suggested approach to program execution allows for selective execution of program parts or tasks provided calculation condition for this part has changed since last time. There only these blocks from entire program are executed whose variables have changed since last calculation. Proposed method can be implemented as software modification or as hardware accelerated solution. The most important part of the idea is task or subprogram triggering condition computation. Methods of program optimization are discussed. In order to determine program blocks that require recalculation in current program scan execution specific hardware support is planned to be researched. Memory content change detection unit allows to determine changes in memory content since last program block execution.

Fast Operating Bit-Byte PLC

Abstract The paper presents a few different approaches to optimizing operation speed of Programmable Logic Controllers. First approach optimizes architecture of the bit-byte CPU, second optimizes program execution, next one data exchange between bit and byte processors and the last one optimizes input/output servicing. All of them lead to a two processors bit-byte architecture, which support of concurrent execution of bit and byte computation tasks. In such architecture the processors can operate without waiting one for the other.

COMPACT PLC WITH EVENT-DRIVEN PROGRAM TASKS EXECUTION

Abstract The paper presents modified idea of program execution in the Programmable Logic Controllers (PLCs). Instead of serial cyclic execution is proposed event sensitive cyclic execution. Proposed approach to program execution allow for selective execution of program blocks or tasks provided calculation condition for this part has changed since last time. Proposed method can be implemented as software modification or as hardware accelerated solution. The most important part of the idea is task or subprogram triggering condition computation. Different method of program optimization are discussed. Finally hardware implementation of event triggered system is presented.

The Dynamic Properties Investigation of the PLC CPU Implemented in FPGA

The paper presents some program examples written and tested to show possibilities of construction of CPUs for PLCs build based on FPGA development platform. Presented unit is optimised for minimum response and throughput time. The constructions are based on bit-word structures of CPU and two types of data (condition) exchange methods: with acknowledge and without acknowledge – in both cases control data are passed through the set of flip-flops. Third unit is built to compare with these two. This unit is simple one processor unit which can execute both - binary and numerical operations. The experiments shown high performances of elaborated CPUs.

Popular microcontrollers execute IEC 61131-3 standard operators and functional blocks in simply automatic control tasks

Over the recent decades a common approach seems to be taken for granted that only dedicated Central Processing Unit (CPU) offered as self-contained modules by various manufacturers are the only solution for implementation of Programmable Logic Controllers (PLC). To demonstrate right the contrary authors of this study reveal various CPU solutions of PLCs developed on the basis of some typical microcontrollers, including the ones from the families MCS-51, AVR and ARM with the Cortex M3 core. These CPUs were then employed to run a control program developed in an Instruction List (IL) language that meets recommendations of the IEC-61131-3 standard. The paper demonstrates that the basic operators of the IL language can be used to simplify bodies of the standard defined function and function blocks. The rules are outlined that the authors adhered to at development of commands for the IL language with dedicated examples that explain how these commands can be used to define functionalities for operational modules of counters and timers and a combinational Boolean function - on the example of the LIMIT procedure. It is also suggested to define several new operators that additionally simplify the notation. The scope of investigations includes also comparison between the solutions suggested by stipulations of the standard in question and the own solutions proposed by the authors with presentation of the outcome from the comparison. The disclosed considerations served as the basis to suggest the new architecture for a CPU that is suitable for operation in line with rules imposed by the standard, but on the other hand it can be used for operation with some modifications suggested by the authors and intended to reduce processing time for some operators, Boolean functions and functional blocks.

About Implementation of IEC 61131-3 IL Operators in Standard Microcontrollers

Abstract The paper presents various solutions for a Central Processing Unit (CPU) of Programmable Logic Controllers (PLC) developed on the basis of three typical microcontrollers from the families MCS- 51, AVR and ARM with the Cortex M3 core. The control program for these CPUs was developed in an Instruction List (IL) language that was in conformity with recommendations of the IEC-61131-3 standard. The most important issue that had to be resolved was translation of original commands in the IL language into own programming languages of the mentioned microcontrollers. The paper demonstrates that the commands of the IL language can be translated into fragments of runtime programs via procedures developed in the C language. The results achieved from all competed experiments make it possible to conclude that it is possible to design an efficient CPU, competitive in terms of the speed and time of the program execution, with use of standard microcontrollers.