Helmut V. Walz

FASTBUS Snoop Diagnostic Module

Development of the FASTBUS Snoop Module, undertaken as part of the prototype program for the new interlaboratory data bus standard, is described. The Snoop Module resides on a FASTBUS crate segment and provides diagnostic monitoring and testing capability. Communication with a remote host computer is handled independent of FASTBUS through a serial link. The module consists of a high-speed ECL front-end to monitor and single-step FASTBUS cycles, a master-slave interface, and a control microprocessor with serial communication ports. Design details and performance specifications of the prototype module are reported.

Status of the SLAC Snoop Diagnostic Module for FASTBUS

A SNOOP Diagnostic Module for FASTBUS is under development at SLAC. The SNOOP Module resides on a FASTBUS crate segment and provides diagnostic monitoring and testing capability. It consists of a high-speed ECL front-end to monitor and single-step segment operations, a simple master interface, and a control processor with two serial communication ports. Module features and specifications are summarized, and prototype hardware is shown.

SLAC FASTBUS Snoop Module-Test Results and Support Software

The development of a diagnostic module for FASTBUS has been completed. The Snoop Module is designed to reside on a Crate Segment and provide high-speed diagnostic monitoring and testing capabilities. Final hardware details and testing of production prototype modules are reported. Features of software under development for a stand-alone single Snoop diagnostic system and Multi-Snoop networks will be discussed.

Progress on the SLAC SNOOP Diagnostic Module for FASTBUS

A SNOOP Diagnostic Module for FASTBUS is under development at SLAC. The SNOOP Module resides on a FASTBUS crate segment and provides diagnostic monitoring and testing capability. It consists of a high-speed ECL front-end to monitor and single-step segment operations, a simple master interface, and a control processor with two serial communication ports. Module features and specifications are summarized, and prototype hardware is shown.

FASTBUS Demonstration Systems

This paper will provide a demonstration of basic FASTBUS hardware and test software. The systems will include single crate segments, simple computer I/O, a fast sequencer and memory, some simple diagnostic and display devices and a UNIBUS to FASTBUS processor interface. The equipment will be set up to show the basic FASTBUS protocols and timing transactions, as well as some of the general initialization software features.

Review of Recent FASTBUS Developments

The status of the FASTBUS Specification for modular data acquisition and control systems is reviewed. Recent developments at research laboratories and available support from commercial manufacturers are highlighted. Covered are hardware developments and system implementations in the U.S.A., Canada and Japan. FASTBUS in Europe and software efforts are described in separate papers at this Conference.

FASTBUS Review 1984

The first year of work with the FASTBUS Specification DOE/ER-0189 for modular high speed data acquisition and control systems is reviewed. FASTBUS system components such as crates, power supplies, modules, and diagnostic tools available from research laboratories and industry in North America and Japan are summarized. New developments and future plans for applications and products are highlighted. European progress on FASTBUS and review of software activities are presented in other papers at this Conference. Relevant background information may be found in the FASTBUS status report presented at the 1983 Nuclear Science Symposium.

Distributed supervisory protection interlock system SLC acceleration

The distributed supervisory protection interlock (DSPI) system is under development at the Stanford Linear Accelerator Center for requirements in the areas of personnel protection, beam containment, and equipment protection interlocks. The DSPI system, distributed over the application site, consists of segments with microprocessor-based controller and I/O (input/output) modules, local area networks for communication, and a global supervisor computer. Segments are implemented with commercially available controller and I/O modules arranged in local interlock clusters, and associated software. Segments provide local interlock data acquisition, processing, and control. Local area networks provide the communication backbone between segments and a global supervisor processor. The supervisor processor monitors the overall system, reports detail status, and provides human interfaces. Details of an R&D test system which will implement the requirements for personnel protection of four typical linear accelerator sectors are presented.<<ETX>>

PASHA-an approach to computer-aided hardware debugging

An interactive computer-aided diagnostic tool for the SLAC (Stanford Linear Accelerator Center) FASTBUS SNOOP has been developed. The distributed software package, written in FORTH and executing concurrently on a IBM PC (personal computer) and on the SNOOP, automatically tests the board and pinpoints faults by running a set of specific tests. Special attention has been given to the menu-driven man-machine interface which guides its use through the debugging session. Details of the design and results of field trials are reported. >

An interactive visual interface for FASTBUS diagnostics

Complex instruments that are not used regularly, such as diagnostic devices, are often avoided or inefficiently used because of the startup effort required to figure out how to apply them. To solve this problem, a visual interface has been developed for the SLACFASTBUS Snoop module. This interface is based on the Macintosh computers standard human interface, using menus, dialogs, and graphics to indicate quickly the range of possibilities and allow easy setup and manipulation of the Snoop modules powerful features. >