David D. Briggs

Competitive 5V-thin and 12V-thick dual gate technology isolated drain LDMOS devices

Integrated power FETs in dc-dc converters should have good CHC rating so the on-resistance of the FETs does not walk outside its guaranteed limits over its intended lifetime thereby increasing the power losses. Planar devices are somewhat limited by CHC physics of gate oxide and drain engineering and not BVdss. The device presented at ISPSD02 was re-engineered in the quest for an isolated FET with BVdss greater than 22V, and meeting the system requirements for a 16V product rating. Data for thin (150 /spl Aring/) and thick gate versions (425 /spl Aring/) of the same device style in a 0.72/spl mu/m technology is presented along with 2D simulation results. The thick gate version shows a slight improvement but not enough to meet the above requirements. Much improved data for a re-engineered device is presented.

A 3V to 6V in, 6A out synchronous buck PWM integrated FET switcher design uses state-of-art power IC technology

A 3V to 6V input, 6A output synchronous buck PWM switcher with integrated FETs; TI code name SWIFT/spl trade/ has been fabricated using a combination of past reported power IC technology. In this IC we extended a production 0.72/spl mu/m technology with enhanced features and then combined mixed circuit design with integrated thin-gate oxide, planar, very-thin-resurf VTR LDMOS FETs. The Power IC uses plated CuNiPd top metal for low resistance busing and bonding over active area and is packaged in a thin line 28 pin TSSOP package having a POWERPAD/spl trade/. The technology combination yields a state-of-art performance power IC. The device is capable of 95% efficiency and is excellent for point-of-load applications such as DSP solutions as well as high density distributed power systems. The key to high efficiency in this product is dual low Ron=30 m/spl Omega/ fets, low gate charge losses, and low reverse recovery losses during power FET switching.