Dale J. Skelton

Modeling and analysis of an off-line battery charger for single cell lithium batteries

Several papers have addressed the issues of modeling and analysis of switching mode converters, but few have targeted systems with a battery load. In this paper, by using the PWM switch model, an analytical model is given for the control loops of an off-line flyback charger. System performance under different charging currents and voltages are analyzed and compared with the resistive load. A real application system is analyzed using the model, and the model prediction is compared with lab measurement.

A 3V to 6V in, 6A out synchronous buck PWM integrated FET switcher design uses state-of-art power IC technology

A 3V to 6V input, 6A output synchronous buck PWM switcher with integrated FETs; TI code name SWIFT/spl trade/ has been fabricated using a combination of past reported power IC technology. In this IC we extended a production 0.72/spl mu/m technology with enhanced features and then combined mixed circuit design with integrated thin-gate oxide, planar, very-thin-resurf VTR LDMOS FETs. The Power IC uses plated CuNiPd top metal for low resistance busing and bonding over active area and is packaged in a thin line 28 pin TSSOP package having a POWERPAD/spl trade/. The technology combination yields a state-of-art performance power IC. The device is capable of 95% efficiency and is excellent for point-of-load applications such as DSP solutions as well as high density distributed power systems. The key to high efficiency in this product is dual low Ron=30 m/spl Omega/ fets, low gate charge losses, and low reverse recovery losses during power FET switching.

Multi-megahertz pulse width modulation converters with improved 1 /spl mu/m p-channel metal oxide semiconductor transistors

Pulse width modulation (PWM) techniques have been limited to 1 to 2 MHz by the switching speeds of currently available power switches. This limitation has been overcome by high speed (<2 nanosecond) switching with improved 1 /spl mu/m PMOS transistors. These devices have been incorporated in a 5 MHz, PWM buck power stage that has demonstrated good efficiency (>85%) and very high power density (500 W/in/sup 3/ versus state-of-the-art 100 W/in/sup 3/).