David I. Sanderson

Quality factor and inductance in differential IC implementations

Monolithic inductors are widely used in microwave ICs and RFICs. Design considerations for inductors on low-resistivity substrates have been described. A /spl pi/-equivalent model, used to account for various loss mechanisms, can be helpful in understanding differences in the definition of L and Q for single-ended and differential structures that exist in the literature. Specific uses for the equations in this article have been outlined. The L and Q for an example monolithic, differential inductor were extracted from measured two-port S-parameters using equations for differential configurations on low-resistivity substrates.

5-6 GHz SiGe VCO with tunable polyphase output for analog image rejection and I/Q mismatch compensation

Image rejection and demodulation quality are adversely affected by in-phase and quadrature (I/Q) channel phase mismatch. This paper presents a 5-6 GHz Silicon Germanium (SiGe) voltage controlled oscillator (VCO) and integrated polyphase filter with I/Q phase imbalance compensation. The design of the VCO is discussed, including considerations for high inductor quality factor (Q) and low VCO phase noise. From a 2.5 V supply, the VCO core consumes 3 mA. The simulated phase noise at 1 MHz from the carrier is -114.6 dBc/Hz. The I/Q imbalance of the polyphase splitter is tunable by means of series output varactors. The polyphase network design can compensate for /spl plusmn/4/spl deg/ I/Q phase imbalance, which could provide approximately 15 dB improvement in image rejection in a Weaver architecture receiver.Image rejection and demodulation quality are adversely affected by in-phase and quadrature (I/Q) channel phase mismatch. This paper presents a 5-6 GHz Silicon Germanium (SiGe) voltage controlled oscillator (VCO) and integrated polyphase filter with I/Q phase imbalance compensation. The design of the VCO is discussed, including considerations for high inductor quality factor (Q) and low VCO phase noise. From a 2.5 V supply, the VCO core consumes 3 mA. The simulated phase noise at 1 MHz from the carrier is -114.6 dBc/Hz. The I/Q imbalance of the polyphase splitter is tunable by means of series output varactors. The polyphase network design can compensate for /spl plusmn/4/spl deg/ I/Q phase imbalance, which could provide approximately 15 dB improvement in image rejection in a Weaver architecture receiver.

Speed and power performance comparison of state-of-the-art CMOS and SiGe RF transistors

DC and RF characteristics of Si nFETs and SiGe HBTs are compared in IBMs leading-edge production RFCMOS and BiCMOS technologies at 90 and 130 nm nodes respectively. Underlying performance trade-offs to achieve low power circuit operation are investigated.

RF FET layout and modeling for design success in RFCMOS technologies

This paper presents challenges in creating high quality RF FET layouts and models in CMOS technologies spanning 0.25 /spl mu/m to 90 nm nodes. The focus is on developing a comprehensive methodology to provide robust, high performance parameterized RF FET layout cells and corresponding scalable RF models to enable RF designs that fully leverage the cost benefit potential of CMOS technology.

Accurate modeling of monolithic inductors using conformal meshing for reduced computation

Accurate component modeling is a key factor to successful wireline and wireless circuit design in Si/SiGe BiCMOS and RF CMOS. This article presents the application of two planar electromagnetic simulation methods for reducing the memory and computation time requirement for accurate simulation of inductors fabricated with thick analog metal layers. First, a conformal subsectioning technique is briefly discussed in the context of reducing the numerical complexity of octagonal and circular spiral inductor analysis. Second, this article discusses a method for determining if more than a two-sheet model of thick metals is needed for accurate inductor simulation. Finally, the conformal mesh is applied to a 3.3-nH inductor fabricated using the IBM 0.13-μm RF CMOS process technology. The simulated and measured results are compared.

Circuit Enablement for SiGe BiCMOS and RFCMOS Technologies

This paper reviews the circuit enablement activity conducted inside IBMs SiGe BiCMOS and RFCMOS technology enablement group. Examples of circuit designs are given. Model/hardware correlations on DC, AC, noise and nonlinearity performance are used to evaluate the BSIM3V3 modeling accuracy. Benchmark circuit example of a VCO is given to demonstrate the technology capabilities which can be used as a reference circuit for customer training, technical support or customer design references

Low phase noise 5 GHz VCOs in 0.13 /spl mu/m SOI and bulk CMOS

This paper present 5 GHz LC VCO designs fabricated in 0.13 mum SOI and bulk CMOS process technologies. Technology advantages, considerations, and trade-offs are compared for high performance VCO design. A methodology for designing a low FOM VCO is given. The SOI VCO achieves a phase noise of -131 dBc/Hz at a 1 MHz offset and consumes 6 mW. The bulk VCO has a phase noise of -132 dBc/Hz at a 1 MHz offset and draws 6.2 mW. Both of these VCOs achieve a FOM value of nearly -200 dBc/Hz

Design considerations for monolithic Si-based RF VCOs in wireless single-chip systems

The paper discusses a number of important considerations in the design of differential VCO known as -G/sub M/ LC-tank VCO in Si technologies. The availability of multiple interconnect layers, culminating in a thick electroplated Cu (bump) layer, has led to significant improvements in the Q-factor of tank circuit inductors. In addition, the use of symmetric differential inductor structures can result in substantial improvements in Q through the enhancement of mutual coupling.