David K. Liu

Scaled dielectric antifuse structure for field-programmable gate array applications

A scaled antifuse structure consisting of a nitride-oxide (NO) dielectric sandwiched between two polysilicon layers is presented. In addition to reducing the effective thickness of the antifuse dielectric, the current conduction asymmetry of the NO layer is also utilized to lower the breakdown voltage to 10.6 V, and consequently the programming voltage to 13.5 V, which is lower than that of previously reported antifuse structures. Time-dependent dielectric breakdown (TDDB) measurements verify that this scaled antifuse structure exhibits a lifetime exceeding ten years (>1*10/sup 12/ s) at 5.5 V in the unprogrammed state. Since a significant fraction of the total measured antifuse resistance is contributed by the sheet resistance of the polysilicon electrodes, this structure also demonstrates the reduction of this resistance component through silicidation of both top and bottom electrodes in the area outside of the antifuse. This poly-poly antifuse structure offers reduction in programmed voltage, reduction in silicon device area, simple peripheral circuitry design, and faster circuit operation due to lower capacitance than previous poly-N/sup +/ antifuse structures.<<ETX>>

A new technique for determining the capacitive coupling coefficients in flash EPROMs

A method for determining the capacitive coupling coefficients of flash erasable programmable read only memories (EPROMs) is introduced. This technique relies on the Fowler-Nordheim erase measurements and source/drain junction leakage characteristics of the device to extract the control gate, source, and drain coupling coefficients. An advantage offered by this method is its use of an actual flash EPROM cell without requiring additional test structures.<<ETX>>

A sublithographic antifuse structure for field-programmable gate array applications

The authors demonstrate an antifuse structure with a cell area of 0.2*0.2 mu m/sup 2/ which is fabricated by using the vertical sidewall of a polysilicon interconnect layer and two-mask patterning and etching steps. The antifuse is constructed in such a way that its vertical dimension is determined by the thickness of the polysilicon layer, and its horizontal dimension is determined by two-mask patterning and etching steps. For a conventional contact-hole type of structure, a 0.2- mu m lithographic capability would be required to achieve the same antifuse cell size. It is also demonstrated that the time-dependent dielectric breakdown (TDDB) reliability of this sidewall antifuse is as good as that of a conventional planar contact-hole antifuse.<<ETX>>

Preoxidation treatment using HCl/HF vapor

Replacement of the conventional two-step sequence of aqueous HF dummy oxide strip and wet clean by a one-step vapor phase HCl/HF/H/sub 2/O strip was investigated. Results indicated improvements in the electrical endurance of grown silicon dioxide and that the vapor mixture containing HCl was effective in reducing the detrimental effects caused by deliberately introduced contaminants. Compared with the conventional wet cleans, a 20% improvement in oxide lifetime was observed. Further improvements should be possible with proper optimization of the quantative composition or the constituents of the vapor.<<ETX>>

Buried source-side injection (BSSI) for flash EPROM programming

A flash-EPROM cell structure that can be programmed at low drain voltages and low power is disclosed. The new element in the device structure is the incorporation of buried junction at the source side where the high electric field region is established during programming. The cell is programmed by hot-electron injection at the source side and erased by Fowler-Nordheim tunneling at the drain side. Typical programming time of 10 mu s/byte can be accomplished with 3.5 V on the drain junction. The structure can be built with the standard EPROM technology and can offer advantages in low-voltage power supply systems such as portable and notebook computers.<<ETX>>