Howard L. Tigelaar

High-performance metal/silicide antifuse (for CMOS technology)

A low-programmed-resistance low-thermal-budget, high-performance metal/silicide antifuse is reported. The programmed ON-State resistance of the metal/silicide antifuse is around 60 Omega , which is a factor of 10 less than that of Si-based antifuses (poly/n/sup +/ and poly/poly). Metal/silicide antifuses also eliminate the nonlinear ON-state resistance seen in Si-based antifuses. Programming of the antifuse can be done in 2 ms at 14 V, which is comparable to Si-based antifuses. Both ON- and OFF-state reliability of the metal/silicide antifuse are shown to be satisfactory.<<ETX>>

Scaled dielectric antifuse structure for field-programmable gate array applications

A scaled antifuse structure consisting of a nitride-oxide (NO) dielectric sandwiched between two polysilicon layers is presented. In addition to reducing the effective thickness of the antifuse dielectric, the current conduction asymmetry of the NO layer is also utilized to lower the breakdown voltage to 10.6 V, and consequently the programming voltage to 13.5 V, which is lower than that of previously reported antifuse structures. Time-dependent dielectric breakdown (TDDB) measurements verify that this scaled antifuse structure exhibits a lifetime exceeding ten years (>1*10/sup 12/ s) at 5.5 V in the unprogrammed state. Since a significant fraction of the total measured antifuse resistance is contributed by the sheet resistance of the polysilicon electrodes, this structure also demonstrates the reduction of this resistance component through silicidation of both top and bottom electrodes in the area outside of the antifuse. This poly-poly antifuse structure offers reduction in programmed voltage, reduction in silicon device area, simple peripheral circuitry design, and faster circuit operation due to lower capacitance than previous poly-N/sup +/ antifuse structures.<<ETX>>

Effects of poly depletion on the estimate of thin dielectric lifetime

Poly-gate depletion during the accelerated time-dependent breakdown (TDDB) test of single-doping-type capacitors (both electrodes of the doping type) results in an overestimate of dielectric lifetime at operation voltage. Simple high-field data extrapolation fails to take into account the voltage-dependent poly band bending. A three-orders-of-magnitude overestimate of lifetime at 5 V for 68-AA oxide equivalent poly/poly capacitors was found. After correcting for the poly depletion effects, the slope of the TDDB projection line decreases by 18%. The effects can be minimized by performing TDDB testing below the top poly inversion voltage. Fermi-Dirac statistics quantitatively explained the phenomenon. Calculated maximum allowable TDDB voltages for different gate doping and oxide thickness are presented as guidelines for test design.<<ETX>>

A sublithographic antifuse structure for field-programmable gate array applications

The authors demonstrate an antifuse structure with a cell area of 0.2*0.2 mu m/sup 2/ which is fabricated by using the vertical sidewall of a polysilicon interconnect layer and two-mask patterning and etching steps. The antifuse is constructed in such a way that its vertical dimension is determined by the thickness of the polysilicon layer, and its horizontal dimension is determined by two-mask patterning and etching steps. For a conventional contact-hole type of structure, a 0.2- mu m lithographic capability would be required to achieve the same antifuse cell size. It is also demonstrated that the time-dependent dielectric breakdown (TDDB) reliability of this sidewall antifuse is as good as that of a conventional planar contact-hole antifuse.<<ETX>>

TDDB on poly-gate single doping type capacitors

Lifetime projections for polycrystalline silicon (poly) gate single doping type capacitors are complicated by gate poly depletion and inversion during the accelerated test. The presence of poly depletion and inversion was experimentally confirmed by CV and IV measurements. Simple high field straight line extrapolation was found to overestimate the 5-V lifetime by 1200 times in the 68-AA oxide equivalent poly/poly capacitors. The overestimate can be minimized by limiting the test voltage below the gate poly inversion voltage. A sensitivity analysis of the overestimate to gate poly doping is also presented.<<ETX>>

A manufacturable 0.30 /spl mu/m gate CMOS technology for high speed microprocessors

A 0.30 /spl mu/m gate CMOS technology for high speed microprocessors with five levels of interconnect is described. A primary challenge in developing a manufacturable 0.30 /spl mu/m gate CMOS process is gate length control. A detailed investigation of the sources of gate length variation using a specially designed testchip is presented. Linewidth control of /spl plusmn/10% is achieved using I-line lithography by applying optical proximity correction to the gate reticle. A high speed cache memory for the target 250 MHz microprocessor product has an access time of 2.02 ns from clock to data out.

Addressing Key Concerns for Implementation of Ni FUSI into Manufacturing for 45/32 nm CMOS

Key remaining concerns raised for implementation of Ni FUSI into manufacturing are addressed and solved suggesting that Ni FUSI is worthy for manufacturing. We studied NiSi, Ni2Si and Ni31Si12 FUSI gates and their showing 1) Excellent reliability (NBTI, PBTI and TDDB) on HfSiON (EOT=1.1nm), with lifetimes >10 years at 1.2 V for optimized HfSiON (BTI similar/improved compared to reference MG, strong effect of N (DPN HfSiON) finding optimal point in NMOS-PMOS BTI trade-off). 2) No Ni penetration into substrate and no additional reliability degradation with multilevel metallization BEOL thermal budget. 3) Excellent mismatch characteristics and low Vt variability down to LG~40nm W-130 nm (no FUSI grain orientation effects), 4) Excellent EOT scalability with no PMOS VFB roll-off down to EOT-0.7 nm (Ni31Si12, WF-4.9 eV); 5) SRAM defectivity analysis finding main type of defects and solutions for their elimination. We also showed 6) phase formation (NiSi, Ni31Si12) similar to blanket films at LG=30 nm.

A novel trench-isolated buried N + FAMOS Transistor suitable for high-density EPROM's

This paper describes an innovative use of trench isolation to achieve high programmability and improved isolation in a high-density electrically programmable read-only memory (EPROM) cell. This cell, with a 13.5-µm2area at 1.5-µm design rules, was fabricated by using a novel cross-point structure with buried N+ (BN+) bit lines as source and drain of the floating-gate avalanche injection MOS (FAMOS) transistor. Programming efficiency and bit-line isolation were enhanced by a novel positioning of the trench isolation between bit-lines and between the double-polysilicon FAMOS transistors. Trench isolation should permit scaling of the bit-line spacing to below 1 µm.

Process windows for convenient in-process monitoring of oxide and polysilicon etches

Process monitor window test structures are developed to standardize and to facilitate the in-process monitoring of oxide and polysilicon etches. With training, the operator can easily monitor and tune the etching process visually using these process windows. If a standard set of process monitor structures is developed for each technology and placed on all reticle sets using that technology, operators are provided with an easily recognized place to make their measurements. These windows standardize the measurement taking process, thereby reducing errors and improving quality.<<ETX>>

Over-estimate of Thin Dielectric Lifetime in Single Doping Type Poly-Gate Capacitors

Summary form only given. It is reported that effects of band-bending produce a voltage drop in the poly gate, which reduces the voltage stress across the capacitor dielectric. It was found that if this effect is not taken into account there is a three-orders-of-magnitude overestimate of the 5-V lifetime for a 68-AA oxide equivalent ONO poly/poly capacitor. A family of curves relating poly doping concentration, dielectric thickness, and the maximum allowable accelerated test voltage was given as guidelines for accelerated time-dependent dielectric breakdown testing. >