Davide Bisi

Deep-Level Characterization in GaN HEMTs-Part I: Advantages and Limitations of Drain Current Transient Measurements

This paper critically investigates the advantages and limitations of the current-transient methods used for the study of the deep levels in GaN-based high-electron mobility transistors (HEMTs), by evaluating how the procedures adopted for measurement and data analysis can influence the results of the investigation. The article is divided in two parts within Part I. 1) We analyze how the choice of the measurement and analysis parameters (such as the voltage levels used to induce the trapping phenomena and monitor the current transients, the duration of the filling pulses, and the method used for the extrapolation of the time constants of the capture/emission processes) can influence the results of the drain current transient investigation and can provide information on the location of the trap levels responsible for current collapse. 2) We present a database of defects described in more than 60 papers on GaN technology, which can be used to extract information on the nature and origin of the trap levels responsible for current collapse in AlGaN/GaN HEMTs. Within Part II, we investigate how self-heating can modify the results of drain current transient measurements on the basis of combined experimental activity and device simulation.

Trapping and Reliability Assessment in D-Mode GaN-Based MIS-HEMTs for Power Applications

This paper reports on an extensive analysis of the trapping processes and of the reliability of experimental AlGaN/GaN MIS-HEMTs, grown on silicon substrate. The study is based on combined pulsed characterization, transient investigation, breakdown, and reverse-bias stress tests, and provides the following, relevant, information: 1) the exposure to high gate-drain reverse-bias may result in a recoverable increase in the on-resistance (RON), and in a slight shift in threshold voltage; 2) devices with a longer gate-drain distance show a stronger increase in RON, compared to smaller devices; 3)current transient measurements indicate the existence of one trap level, with activation energy of 1.03 ± 0.09 eV; and 4) we demonstrate that through the improvement of the fabrication process, it is possible to design devices with negligible trapping. Furthermore, the degradation of the samples was studied by means of step-stress experiments in off-state. Results indicate that exposure to moderate-high reverse bias (<; 250 V for LGD = 2 μm) does not induce any measurable degradation, thus confirming the high reliability of the analyzed samples. A permanent degradation is detected only for very high reverse voltages (typically, VDS = 260-265 V, on a device with LGD = 2 μm stressed with VGS = - 8 V) and consists of a rapid increase in gate leakage current, followed by a catastrophic failure. EL measurements and microscopy investigation revealed that degradation occurs close to the gate, in proximity of the sharp edges of the drain contacts, i.e., in a region where the electric field is maximum.

Kinetics of Buffer-Related RON-Increase in GaN-on-Silicon MIS-HEMTs

This letter reports an extensive analysis of the charge capture transients induced by OFF-state bias in double heterostructure AlGaN/GaN MIS- high electron mobility transistor grown on silicon substrate. The exposure to OFF-state bias induces a significant increase in the ON-resistance (Ron) of the devices. Thanks to time-resolved on-the-fly analysis of the trapping kinetics, we demonstrate the following relevant results: 1) Ron-increase is temperature- and field-dependent, hence can significantly limit the dynamic performance of the devices at relatively high-voltage and high temperature (100 °C-140 °C) operative conditions; 2) the comparison between OFF-state and back-gating stress indicates that the major contribution to the Ron-increase is due to the trapping of electrons in the buffer, and not at the surface; 3) the observed exponential kinetics suggests the involvement of point-defects, featuring thermally activated capture cross section; and 4) trapping-rate is correlated with buffer vertical leakage-current and is almost independent to gate-drain length.

Buffer Traps in Fe-Doped AlGaN/GaN HEMTs: Investigation of the Physical Properties Based on Pulsed and Transient Measurements

This paper presents an extensive investigation of the properties of the trap with activation energy equal to 0.6 eV, which has been demonstrated to be responsible for current collapse (CC) in AlGaN/GaN HEMTs. The study was carried out on AlGaN/GaN HEMTs with increasing concentration of iron doping in the buffer. Based on pulsed characterization and drain current transient measurements, we demonstrate that for the samples under investigation: 1) increasing concentrations of Fe-doping in the buffer may induce a strong CC, which is related to the existence of a trap level located 0.63 eV below the conduction band energy and 2) this trap is physically located in the buffer layer, and is not related to the iron atoms but-more likely-to an intrinsic defect whose concentration depends on buffer doping. Moreover, we demonstrate that this level can be filled both under OFF-state conditions (by gate-leakage current) and under ON-state operation (when hot electrons can be injected to the buffer): for these reasons, it can significantly affect the switching properties of AlGaN/GaN HEMTs.

Temperature-Dependent Dynamic

This paper reports an investigation of the trapping mechanisms responsible for the temperature-dependent dynamic-RON of GaN-based metal-insulator-semiconductor (MIS) high electron mobility transistors (HEMTs). More specifically, we perform the following. First, we propose a novel testing approach, based on combined OFF-state bias, backgating investigation, and positive substrate operation, to separately investigate the buffer-and the surface-related trapping processes. Then, we demonstrate that the dynamic RON of GaN-based MIS-HEMTs significantly increases when the devices are operated at high temperature levels. We explain this effect by demonstrating that it is due to the increased injection of electrons from the substrate to the buffer (under backgating conditions) and from the gate to the surface (under positive substrate operation). Finally, we demonstrate that by optimizing the buffer and by reducing the vertical leakage, substrate-related trapping effects can be completely suppressed. The results described within this paper provide general guidelines for the evaluation of the origin of dynamic RON in GaN power HEMTs and point out the important role of the buffer leakage in favouring the trapping processes.

R_{\mathrm {\mathrm{{\scriptstyle ON}}}}

This paper describes an extensive analysis of the role of off-state and semi-on state bias in inducing the trapping in GaN-based power High Electron Mobility Transistors. The study is based on combined pulsed characterization and on-resistance transient measurements. We demonstrate that—by changing the quiescent bias point from the off-state to the semi-on state—it is possible to separately analyze two relevant trapping mechanisms: (i) the trapping of electrons in the gate-drain access region, activated by the exposure to high drain bias in the off-state; (ii) the trapping of hot-electrons within the AlGaN barrier or the gate insulator, which occurs when the devices are operated in the semi-on state. The dependence of these two mechanisms on the bias conditions and on temperature, and the properties (activation energy and cross section) of the related traps are described in the text.

in GaN-Based MIS-HEMTs: Role of Surface Traps and Buffer Leakage

Slow trapping phenomenon in AlGaN/GaN HEMTs has been extensively analyzed and described in this paper. Thanks to a detailed investigation, based on a combined pulsed and transient investigation of the current/voltage characteristics (carried out over on an 8-decade time scale), we report a detailed description of the properties of trap levels located in the gate–drain surface, and in the region under the gate of AlGaN/GaN HEMTs. More specifically, the following, relevant results have been identified: (i) the presence of surface trap states may determine a significant current collapse, and reduction of the peak transconductance. During a current transient measurement, the emission of electrons trapped at surface states proceeds through hopping, as demonstrated by means of temperature-dependent measurements. The activation energy of the de-trapping process is equal to 99 meV. (ii) The presence of a high density of defects under the gate may induce a significant shift in the threshold voltage, when devices are submitted to pulsed transconductance measurements. The traps responsible for this process have an activation energy of 0.63 eV, and are detected only on samples with high gate leakage, since gate current allows for a more effective charging/de-charging of the defects.

Trapping in GaN-based metal-insulator-semiconductor transistors: Role of high drain bias and hot electrons

This letter reports an in-depth study of the negative threshold voltage instability in GaN-on-Si metal-insulator-semiconductor high electron mobility transistors with partially recessed AlGaN. Based on a set of stress/recovery experiments carried out at several temperatures, we demonstrate that: 1) operation at high temperatures and negative gate bias (-10 V) may induce a significant negative threshold voltage shift, that is well correlated to a decrease in on-resistance; 2) this process has time constants in the range between 10-100 s, and is accelerated by temperature, with activation energy equal to 0.37 eV; and 3) the shift in threshold voltage is recoverable, with logarithmic kinetics. The negative shift in threshold voltage is ascribed to the depletion of trap states located at the SiN/AlGaN interface and/or in the gate insulator.

Trapping phenomena in AlGaN/GaN HEMTs: a study based on pulsed and transient measurements

Despite the potential of GaN-based power transistors, these devices still suffer from certain parasitic and reliability issues that limit their static and dynamic performance and the maximum switching frequency. The aim of this paper is to review our most recent results on the parasitic mechanisms that affect the performance of GaN-on-Si HEMTs; more specifically, we describe the following relevant processes: (i) trapping of electrons in the buffer, which is induced by off-state operation; (ii) trapping of hot electrons, which is promoted by semi-on state operation; (iii) trapping of electrons in the gate insulator, which is favored by the exposure to positive gate bias. Moreover, we will describe one of the most critical reliability aspects of Metal-Insulator-Semiconductor HEMTs (MIS-HEMTs), namely time-dependent dielectric breakdown.

Negative Bias-Induced Threshold Voltage Instability in GaN-on-Si Power HEMTs

Abstract This paper reports an extensive analysis of the trapping and reliability issues in AlGaN/GaN metal insulator semiconductor (MIS) high electron mobility transistors (HEMTs). The study was carried out on three sets of devices with different gate insulators, namely PEALD SiN, RTCVD SiN and ALD Al 2 O 3 . Based on combined dc, pulsed and transient measurements we demonstrate the following: (i) the material/deposition technique used for the gate dielectric can significantly influence the main dc parameters (threshold current, subthreshold slope, gate leakage) and the current collapse; and (ii) current collapse is mainly due to a threshold voltage shift, which is ascribed to the trapping of electrons at the gate insulator and/or at the AlGaN/insulator interface. The threshold voltage shift (induced by a given quiescent bias) is directly correlated to the leakage current injected from the gate; this demonstrates the importance of reducing gate leakage for improving the dynamic performance of the devices. (iii) Frequency-dependent capacitance–voltage (C–V) measurements demonstrate that optimized dielectric allow to lower the threshold-voltage hysteresis, the frequency dependent capacitance dispersion, and the conductive losses under forward-bias. (iv) The material/deposition technique has a significant impact on device robustness against gate positive bias stress. Time to failure is Weibull-distributed with a beta factor not significantly influenced by the properties of the gate insulator. The results presented within this paper provide an up-to-date overview of the main advantages and limitations of GaN-based MIS HEMTs for power applications, on the related characterization techniques and on the possible strategies for improving device performance and reliability.