Debashis Mandal

1 V CMOS instrumentation amplifier with high DC electrode offset cancellation for ECG acquisition systems

A new circuit topology for a low voltage, low noise instrumentation amplifier (IA) applicable for electrocardiogram signal acquisition system is designed. This circuit is based on the current feedback topology, which is implemented using folded cascode structure at both input and output stages. This helps to sense very low common mode voltage. Achieved input common mode range (ICMR) is 71.43 – 700 mV. DC electrode offset cancellation circuit is realized to remove DC electrode offset along with the low frequency noise. The IA can withstand a high DC electrode offset of ±18 mV. It also has a wide input dynamic range of ±1 µV to ±1 mV. The voltage gain is around 38 dB. It consumes 110 µW power with a supply voltage of 1 V. A high common mode rejection ratio (CMRR) of 80 dB is achieved. The integrated input referred noise is 1.64 µVrms (0.1 Hz – 150 Hz). This design is implemented in 0.18 µm standard CMOS process.

7.95mW 2.4GHz Fully-Integrated CMOS Integer N Frequency Synthesizer

A fully-integrated, ZigBee standard compliant, frequency synthesizer in the frequency range of 2.4-2.4835 GHz with frequency resolution of 5MHz, is designed in 0.18mum epi-CMOS process and silicon performance is measured. Integer-N architecture is chosen for implementation. It consumes 7.95mW of power at 1.8V supply and core area is 0.75times0.65mm2. The measured phase-noises are -81.55dBc/Hz and -108.55dBc/Hz at 100kHz and 1MHz offset, respectively, with low settling time less than 25mus

Spur suppression in frequency synthesizer using switched capacitor array

In this paper we propose a PLL based frequency synthesizer architecture having low spur. Using an array of switched capacitors and a delay locked loop (DLL), a periodic charge distribution technique to suppress reference spur in the PLL has been adopted. The DLL provides the equispaced M instances at which the capacitor array distributes the charge. For the validation of the concept, an integer-N frequency synthesizer with four times repetition of ripples for 916 MHz output frequency and 2 MHz input reference frequency, has been designed in 180 nm CMOS technology. Cadence Spectre simulation shows output spur improvement, with respect to a conventional architecture, of about 59, 75 and 65 dB respectively at 2, 4, 6 MHz offset frequencies while the spur at 8 MHz offset remains unchanged.

A CMOS instrumentation amplifier with low voltage and low noise for portable ECG monitoring systems

A low voltage, low noise instrumentation amplifier (IA) applicable for Electrocardiogram signal acquisition system has been designed. The circuit is based on the current feedback topology which has been implemented using folded cascode structure at the input stage. It works at zero input common mode voltage with 1V supply. It has a wide input dynamic range of plusmn0.01 mV to plusmn1.2 mV. The voltage gain is 45 dB and it consumes 165 muW power. A high common mode rejection ratio (CMRR) of 125 dB has been achieved. The integrated input referred noise is 3 muVrms (0.2Hz - 150 Hz). The design has been done in 0.18 mum standard CMOS process.

A 100-mA, 99.11% Current Efficiency, 2-mV pp Ripple Digitally Controlled LDO With Active Ripple Suppression

Digital low-dropout (DLDO) regulators are gaining attention due to their design scalability for distributed multiple voltage domain applications required in state-of-the-art system-on-chips. Due to the discrete nature of the output current and the discrete-time control loop, the steady-state response of the DLDO has inherent output voltage ripple. A hybrid DLDO (HD-LDO) with fast response and stable operation across a wide load range while reducing the output voltage ripple is proposed. In the HD-LDO, a DLDO and a low current analog ripple cancelation amplifier (RCA) work in parallel. The output dc of the RCA is sensed by a 2-bit analog-to-digital converter, and the digitized linear stage current is fed into the DLDO as an error signal. During load transients, a gear-shift controller enables fast transient response using dynamic load estimation. The DLDO suppresses the output dc of the RCA within its current resolution. With this arrangement, a majority of the dc load current is provided by the DLDO and the RCA supplies ripple cancelation current. The HD-LDO is designed and fabricated in a 180-nm CMOS technology, and occupies 0.697 mm2 of the die area. The HD-LDO operates with an input voltage range of 1.43–2.0 V and an output voltage range of 1.0–1.57 V. At 100-mA load current, the HD-LDO achieves a current peak efficiency of 99.11% and a settling time of 15 clock periods with a 0.5-MHz clock for a current switching between 10 and 90 mA. The RCA suppresses fundamental, second, and third harmonics of the switching frequency by 13.7, 13.3, and 14.1 dB, respectively.

Adaptive integrated CMOS circulator

An adaptive circulator fabricated on a 130 nm CMOS is presented. Circulator has two adaptive blocks for gain and phase mismatch correction and leakage cancelation. The impedance matching circuit corrects mismatches for antenna, divider, and LNTA. The cancelation block cancels the Tx leakage. Measured isolation between transmitter and receiver for single tone at 2.4 GHz is 90 dB, and for a 40 MHz wide-band signal is 50dB. The circulator Rx gain is 10 dB, with NF = 4.7 dB and 5 dB insertion loss.

PV panel power optimization using sub-panel MPPT

Photo-voltaic systems are affected by converter losses, partial shading and other mismatches in the panels. This paper presents a sub-panel maximum power point tracking that removes the bypass diodes of the panels to optimize the individual sub-panels. Compared to the panel maximum power point tracking, the sub-panel maximum power point tracking reduces the mismatches, losses and increases the output power of the system. The design was implemented in a prototype board and tested to verify its performance. The sub-panel level power optimization improves the output power of a shaded panel by up to 20%, compared to panel MPPT with internal bypass diodes.

A 1.3–2.4-GHz 3.1-mW VCO Using Electro-Thermo- Mechanically Tunable Self-Assembled MEMS Inductor on HR Substrate

This paper reports implementation and wafer-level testing of a self-assembled tunable microelectromechanical systems (MEMS) inductor with electrostatic, electrothermal, and thermal tuning capability. The surface micromachined inductor was fabricated on a high-resistivity (HR) substrate ( ρ = 5 kΩ·cm) using a doped polysilicon and Au-Cr metal combination as a bimorph structural layer for providing self-assembled elevation with an enhanced Q factor. Extensive electro-thermo-mechanical and RF characterization was carried out for the inductor, the latter over a temperature range from -30 °C to 150 °C. Furthermore, the tunable inductor was integrated in the tank circuit of a CMOS oscillator and wafer-level MEMS-CMOS voltage-controlled oscillator testing revealed a best figure-of-merit of -197.6 dB with a frequency tuning range of 1.3-2.4 GHz with a power consumption of 3.07 mW.

Development of a wireless integrated toxic and explosive MEMS based gas sensor

Demand of strict environmental safety norms in mines, industries leads to the development of smart sensor systems for monitoring the explosive and toxic gases like methane (CH/sub 4/) and carbon monoxide (CO). In the present work a wireless integrated CH/sub 4/ and CO gas sensor with a unique transmission scheme has been proposed. It detects CH/sub 4/ & CO gas and generates frequency modulated (FM) signal in two distinct frequency bands in the range of 2.5823 GHz to 2.5542 GHz for CH/sub 4/ concentration from 1% to 2.5% in air and 2.4854 GHz to 2.404 GHz for CO concentration from 50ppm to 300ppm. Also it transmits the generated FM signal through antenna. The receiver section demodulates the signal and displays the gas concentration.

Disturbance-free BIST for loop characterization of DC-DC buck converters

Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to their high efficiency. Unfortunately, they are also subject to higher process variations jeopardizing stable operation of the power supply. This paper presents a technique to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation using a white noise based excitation and correlation. White noise excitation is generated via pseudo random disturbance at reference and PWM input of the converter with the test signal energy being spread over a wide bandwidth, below the converter noise and ripple floor. Test signal analysis is achieved by correlating the pseudo random input sequence with the output response and thereby accumulating the desired behavior over time and pulling it above the noise floor of the measurement set-up. An off-the-shelf power converter, LM27402 is used as the DUT for the experimental verification. Experimental results show that the proposed technique can estimate converters natural frequency and Q-factor within ±2.5% and ±0.7% error margin respectively, over changes in load inductance and capacitance.