Steve Stoffels

Trapping and Reliability Assessment in D-Mode GaN-Based MIS-HEMTs for Power Applications

This paper reports on an extensive analysis of the trapping processes and of the reliability of experimental AlGaN/GaN MIS-HEMTs, grown on silicon substrate. The study is based on combined pulsed characterization, transient investigation, breakdown, and reverse-bias stress tests, and provides the following, relevant, information: 1) the exposure to high gate-drain reverse-bias may result in a recoverable increase in the on-resistance (RON), and in a slight shift in threshold voltage; 2) devices with a longer gate-drain distance show a stronger increase in RON, compared to smaller devices; 3)current transient measurements indicate the existence of one trap level, with activation energy of 1.03 ± 0.09 eV; and 4) we demonstrate that through the improvement of the fabrication process, it is possible to design devices with negligible trapping. Furthermore, the degradation of the samples was studied by means of step-stress experiments in off-state. Results indicate that exposure to moderate-high reverse bias (<; 250 V for LGD = 2 μm) does not induce any measurable degradation, thus confirming the high reliability of the analyzed samples. A permanent degradation is detected only for very high reverse voltages (typically, VDS = 260-265 V, on a device with LGD = 2 μm stressed with VGS = - 8 V) and consists of a rapid increase in gate leakage current, followed by a catastrophic failure. EL measurements and microscopy investigation revealed that degradation occurs close to the gate, in proximity of the sharp edges of the drain contacts, i.e., in a region where the electric field is maximum.

Kinetics of Buffer-Related RON-Increase in GaN-on-Silicon MIS-HEMTs

This letter reports an extensive analysis of the charge capture transients induced by OFF-state bias in double heterostructure AlGaN/GaN MIS- high electron mobility transistor grown on silicon substrate. The exposure to OFF-state bias induces a significant increase in the ON-resistance (Ron) of the devices. Thanks to time-resolved on-the-fly analysis of the trapping kinetics, we demonstrate the following relevant results: 1) Ron-increase is temperature- and field-dependent, hence can significantly limit the dynamic performance of the devices at relatively high-voltage and high temperature (100 °C-140 °C) operative conditions; 2) the comparison between OFF-state and back-gating stress indicates that the major contribution to the Ron-increase is due to the trapping of electrons in the buffer, and not at the surface; 3) the observed exponential kinetics suggests the involvement of point-defects, featuring thermally activated capture cross section; and 4) trapping-rate is correlated with buffer vertical leakage-current and is almost independent to gate-drain length.

Reliability and parasitic issues in GaN-based power HEMTs: a review

Despite the potential of GaN-based power transistors, these devices still suffer from certain parasitic and reliability issues that limit their static and dynamic performance and the maximum switching frequency. The aim of this paper is to review our most recent results on the parasitic mechanisms that affect the performance of GaN-on-Si HEMTs; more specifically, we describe the following relevant processes: (i) trapping of electrons in the buffer, which is induced by off-state operation; (ii) trapping of hot electrons, which is promoted by semi-on state operation; (iii) trapping of electrons in the gate insulator, which is favored by the exposure to positive gate bias. Moreover, we will describe one of the most critical reliability aspects of Metal-Insulator-Semiconductor HEMTs (MIS-HEMTs), namely time-dependent dielectric breakdown.

Trapping and reliability issues in GaN-based MIS HEMTs with partially recessed gate

Abstract This paper reports an extensive analysis of the trapping and reliability issues in AlGaN/GaN metal insulator semiconductor (MIS) high electron mobility transistors (HEMTs). The study was carried out on three sets of devices with different gate insulators, namely PEALD SiN, RTCVD SiN and ALD Al 2 O 3 . Based on combined dc, pulsed and transient measurements we demonstrate the following: (i) the material/deposition technique used for the gate dielectric can significantly influence the main dc parameters (threshold current, subthreshold slope, gate leakage) and the current collapse; and (ii) current collapse is mainly due to a threshold voltage shift, which is ascribed to the trapping of electrons at the gate insulator and/or at the AlGaN/insulator interface. The threshold voltage shift (induced by a given quiescent bias) is directly correlated to the leakage current injected from the gate; this demonstrates the importance of reducing gate leakage for improving the dynamic performance of the devices. (iii) Frequency-dependent capacitance–voltage (C–V) measurements demonstrate that optimized dielectric allow to lower the threshold-voltage hysteresis, the frequency dependent capacitance dispersion, and the conductive losses under forward-bias. (iv) The material/deposition technique has a significant impact on device robustness against gate positive bias stress. Time to failure is Weibull-distributed with a beta factor not significantly influenced by the properties of the gate insulator. The results presented within this paper provide an up-to-date overview of the main advantages and limitations of GaN-based MIS HEMTs for power applications, on the related characterization techniques and on the possible strategies for improving device performance and reliability.

Investigation of the p-GaN Gate Breakdown in Forward-Biased GaN-Based Power HEMTs

In this letter, we report a detailed experimental investigation of the time-dependent breakdown induced by forward gate stress in GaN-based power HEMTs with a p-type gate, controlled by a Schottky metal/p-GaN junction. When a high stress voltage is applied on the gate, a large voltage drop and an electric field occur in the depletion region of the p-GaN close to the metal interface, promoting the formation of a percolation path. We have investigated the mechanisms underlying the gate breakdown by adopting different stress conditions, analyzing the influence of the temperature, and investigating the activation energy of the traps. In addition, thanks to this approach, the device lifetime has been evaluated and an original empirical model, representing the relationship between the gate leakage current and the time to failure, has been proposed.

Direct comparison of GaN-based e-mode architectures (recessed MISHEMT and p-GaN HEMTs) processed on 200mm GaN-on-Si with Au-free technology

Gallium nitride transistors are going to dominate the power semiconductor market in the coming years. The natural form of GaN-based devices is “normally-on” or depletion mode (d-mode). Despite these type of devices can be used in power semiconductor systems by means of special drivers or in a cascode package solution, yet the market demands for normally-off or enhancement mode (e-mode) devices. In this work, we directly compare and analyze the two most common approaches to obtain GaN-based e-mode devices: recessed gate MISHEMTs and p-GaN HEMTs. Both approaches have their pro’s and con’s as well as their critical process steps.

Stability evaluation of Au-free Ohmic contacts on AlGaN/GaN HEMTs under a constant current stress

Abstract The reliability of Au-free Ohmic contacts has been evaluated under a constant current stress (500xa0mA/mm) in a high temperature environment (150xa0°C, 175xa0°C, and 200xa0°C). Two Ohmic contact schemes with different Ti/Al thicknesses (5xa0nm/100xa0nm and 10xa0nm/100xa0nm) have been tested. The results showed that the degradation of the resistance (Rincrease) is accelerated at a higher temperature condition. Moreover, Rincrease has a square root dependence with the time. This indicates that a diffusion process could be responsible for the observed degradation. This has been confirmed by means of physical failure analyses (FIB/TEM) performed on a highly degraded device: an apparent roughness of the interface between TiN and the Ohmic metal layer was observed. On top of this, Nitrogen out-diffusion into the Ohmic metal was observed in the EDS/EELS analyses, suggesting that a material diffusion phenomenon might play a role. In addition, we observed that the devices with a lower initial contact resistance (Rc) showed lower degradation with respect to devices with a larger initial Rc. This suggests that obtaining lower Rc is beneficial not only for the performance but also for the reliability.

Degradation of GaN-HEMTs with p-GaN Gate: Dependence on temperature and on geometry

This paper investigates the time-dependent degradation of normally-off transistors with p-GaN gate submitted to constant voltage stress. Based on combined dc characterization and temperature-dependent analysis, we study the dependence of time-to-failure on stress temperature and device geometry. The results of this analysis indicate that: (i) normally-off transistors with p-GaN gate have a good stability, reaching a 20 years lifetime with a 7.2 V gate bias; (ii) at higher stress voltages, a time-dependent failure is observed. Time-to-failure (TTF) depends exponentially on stress voltage, while failure is ascribed to a localized breakdown process that takes place in the p-GaN/AlGaN stack; (iii) TTF scales with device area only if the area is changed by increasing the gate width (and not if area is increased by modifying gate length). This result suggests that degradation occurs mostly in proximity of the gate edge, rather than at the center of the gate. (iv) finally, stress tests carried out at different temperature levels indicate that TTF is dependent on temperature, with activation energy of 0.48–0.50 eV.

Reliability of Au-Free AlGaN/GaN-on-Silicon Schottky Barrier Diodes Under ON-State Stress

In this paper, we report the results of an experimental analysis of the degradation induced by ON-state stress in GaN-based Schottky barrier diodes (SBDs). When a high stress current is applied to the device, turn-ON voltage (VTON), forward voltage (VF), and ON-resistance (RON) are affected by charge carrier trapping occurring at the AlGaN surface close to the anode corners and/or into the AlGaN barrier layer. We have investigated the degradation of SBDs under different stress conditions, analyzing the influence of temperature and voltage, investigating the activation energy of the traps, and hence the trapping mechanisms. In addition, thanks to this approach, the device lifetime has been evaluated, proving good device reliability.

ON-State Degradation in AlGaN/GaN-on-Silicon Schottky Barrier Diodes: Investigation of the Geometry Dependence

In this paper, we present the results of a combined measurement/simulation analysis of the degradation induced by on-state stress in Au-free AlGaN/gallium-nitride-on-Si Schottky barrier diodes (SBDs). Turn-on voltage (VTON) and on-resistance (RON) are affected by charge carrier trapping/detrapping, occurring in different regions and caused by different mechanisms, when a high stress current is applied to the device. In particular, we have investigated the degradation of SBDs adopting different stress conditions and analyzing the influence of the diode geometry; consequently, we were able to identify the physical mechanisms responsible for long-term degradation of VTON and RON. In addition, thanks to this approach, a critical electric field for the RON degradation has been determined.