Denis Shamiryan

Improving mechanical robustness of ultralow-k SiOCH plasma enhanced chemical vapor deposition glasses by controlled porogen decomposition prior to UV-hardening

We report a new curing procedure of a plasma enhanced chemical vapor deposited SiCOH glasses for interlayer dielectric applications in microelectronic. It is demonstrated that SiOCH glasses with improved mechanical properties and ultralow dielectric constant can be obtained by controlled decomposition of the porogen molecules used to create nanoscale pores, prior to the UV-hardening step. The Young’s modulus (YM) of conventional SiOCH-based glasses with 32% open porosity hardened with porogen is 4.6 GPa, this value is shown to increase up to 5.2 GPa with even 46% open porosity, when the glasses are hardened after porogen removal. This increase in porosity is accompanied by significant reduction in the dielectric constant from 2.3 to 1.8. The increased YM is related to an enhanced molecular-bridging mechanism when film is hardened without porogen that was explained on the base of percolation of rigidity theory and random network concepts.

The Importance of Cavitation Hysteresis in Megasonic Cleaning

An improved fundamental understanding of the megasonic cleaning process is necessary to optimize cleaning efficiency and minimize the unwanted damage to fragile structures. Argon sonoluminescence (SL) measurements are done to achieve an improved insight in the collapse threshold and behavior of microbubbles. This paper reports on acoustic cavitation by means of Ar Sonoluminescence (SL) investigation achieved with a dedicated test cell, a photomultiplier tube (PMT) and a gasification system. The results show an increase in SL signal as a function of the applied acoustic power density. An increase in Ar concentration results in a decrease in SL signal. Furthermore, a clear hysteretic behavior in the SL signal is identified when ramping the acoustic power up and down. This hysteresis effect can be attributed to the nucleation of bubbles during the increasing branch of the power loop. Finally the time evolution of SL light after the switching on of the acoustic transducers revealed the existence of a delay time.

Plasma Etching: From Micro- to Nanoelectronics

The role of plasma etching in the semiconductor technology upon switching from the microscale to the nanoscale dimensions is discussed. The continuing miniaturization has led to impossibility of simple scaling and further use of the conventional materials of silicon microelectronics. New materials and functional elements of integrated circuits call for revision of the existing plasma etching processes and development of novel processes. This situation brings plasma etching along with photolithography to the forefront of nanoelectronics technology.

Galvanic Corrosion of Stacked Metal Gate Electrodes during Cleaning in HF Solutions

According to the ITRS Roadmap [1], new dielectric and metal gate materials will be required for high performance and low stand-by power applications at the 45 nm technology node and beyond. Currently, many candidate materials are under investigation. Based on the state-of-the-art [2,3,4], some of the most likely candidates to be used as metal gate electrodes include TiN, TaN, Mo and Ru. To address the workfunction tuning issue in this future generation of transistors, a possible approach is to use a metal layer on the high-k dielectric to control the workfunction and a conductor material on top to make the gate electrical contact (fig. 1). As a result, it creates a risk of galvanic enhanced corrosion at the gate electrode level during wet cleaning. We have studied galvanic coupling between the dissimilar materials of the gate electrode (TiN, Mo, Ru, PolySilicon). The study focuses on diluted HF mixtures, which in general show overall better compatibility with metal gates than strong oxidizing chemistries. Diluted HF based mixtures are used for residual high-k removal and post-etch residues removal [5]. In addition, it is also used for removal of oxide hardmask after etching of the metal gate stack.

Post Extension Ion Implant Photo Resist Strip for 32 nm Technology and beyond

The most advanced technology nodes require ultra shallow extension implants (low energy) which are very vulnerable to ash related substrate oxidation, silicon and dopant loss, which can result in a dramatic increase of the source/drain resistance and shifted transistor threshold voltages. A robust post extension ion implant ash process is required in order to meet cleanliness, near zero Si loss and dopant loss specifications. This paper discusses a performance comparison between fluorine-free, reducing and oxidizing, ash chemistries and “as implanted – no strip” process conditions, for both state-of-the-art nMOS and pMOS implanted fin resistors. Fluorine-free processes were chosen since earlier experiments with fluorine containing plasma strips exhibited almost a 10x increase in sheet resistance in the worse case.

Influence of TaN Gate Electrode Microstructure on Its Dry Etch Properties

The etch properties of physical vapor deposited TaN used as a metal gate electrode have been found to be dependent on its crystalline microstructure. As found by X-ray diffraction, the initially amorphous TaN crystallizes at temperatures above 500°C. The crystallization results in lower resistivity (decreased by 13%), and lower etch rate in BCl 3 plasma (decreased by 24%). The different crystalline microstructure can manifest itself in different etch results when the same etch process is applied for gate stacks that contain the same TaN but were subjected to different thermal budget.

LOW SUBSTRATE DAMAGE HIGH-K REMOVAL AFTER GATE PATTERNING

2materials, a high-k removal process selective towards the Si substrate should be developed. High-k can be removed dry or wet. Dry removal (by plasma etch) is anisotropic (do not create an undercut in the high-k layer under the gate) but might damage the Si substrate. Wet removal could bring little or no damage to the substrate but creates an undercut due to its isotropic nature. Moreover, a crystallized (upon anneal) high-k can be hardly removed by wet treatment. For the Hf-based high-k materials (HfO2 and Hf silicate with various Hf content) we propose a combi 1 ned removal approach: first the high-k is etched away partially dry (down to approx. 1 nm) by BCl3 plasma, then the remaining plasma damaged layer is removed wet by an HF/HCl water solution. Such an approach combines advantages of both dry and wet removal techniques.

Influence of Photoresist and BARC Selection on the Efficiency of a Post-Etch Wet Strip in BEOL Applications

All-wet processes are gaining a renewed interest for the removal of post-etch photoresist (PR) and Bottom AntiReflective Coating (BARC) in the back-end-of-line (BEOL) semiconductor manufacturing, as plasma ash, traditionally used to remove the PR and BARC layer after etch, cause damage to the low-k dielectric. This study investigates the modification of 193 nm post-etch PR and BARC layer by UV irradiation, that can be used as an intermediate step to enhance PR and BARC wet strip by O3/H2O.

Wafer backside cleaning strategies for high-k/metal gate processing

In this work the removal of different metallic and particulate contaminants relevant for high-k/metal gate processing is studied. Best cleaning efficiency of both silicon and nitride substrates is achieved using a HF/HNO3-based cleaning resulting in a particle removal efficiency higher than 90% and metal removal down to 1010 at/cm2.

Revealing the Porous Structure of Low-k Materials Through Solvent Diffusion

We propose a simple and effective method for studying the porous structure of a thin film. The method is based on the observation of lateral diffusion of solvents inside a porous film using an optical microscope. The diffusion coefficients of solvents calculated from such observations can be used for revealing the pore interconnection structure of the porous film in question.