Eddy Kunnen

Effect of energetic ions on plasma damage of porous SiCOH low-k materials

Plasma damage of SiCOH low-k films in an oxygen plasma is studied using a transformer coupled plasma reactor. The concentration of oxygen atoms and O2+ ions is varied by using three different conditions: (1) bottom power only, (2) bottom and top power, and (3) top power only. After plasma exposure, the low-k samples are characterized by various experimental techniques. It is shown that the ion bombardment induced by the bottom power minimizes the plasma damage by increasing the recombination coefficient of oxygen radicals. Contrary to the expectations, the densification of the top surface by ion radiation was limited. The increase in the recombination coefficient is mainly provided by modification of the pore wall surface and creation of chemically active sites stimulating the recombination of oxygen atoms. The results show that a reduction in plasma damage can be achieved without sealing of low-k top surface.

A way to integrate multiple block layers for middle of line contact patterning

It is clear today that further scaling towards smaller dimensions and pitches requires a multitude of additional process steps. Within this work we look for solutions to achieve a middle of line 193i based patterning scheme for N7 logic at a contacted poly pitch of 40-45 nm. At these pitches, trenches can still be printed by means of double patterning. However, they need to be blocked at certain positions because of a limited line end control below 90 nm pitch single print. Based on the 193i patterning abilities, the proposed SRAM (Static Random Access Memory) cell requires 5 blocking layers. Integrating 5 blocking layers is a new challenge since down to N10 one blocking layer was usually sufficient. The difficulty with multiple blocking layers is the removal of the masked parts, especially in cases of overlap. As a solution a novel patterning approach is proposed and tried out on relaxed dimensions (patent pending). The proposed solution is expected not to be sensitive to the number of blocking layers used, and tolerates their overlap. The stack is constructed to be compatible with N7 substrates such as SiGe or P:Si. Experimental results of the stack blocking performance on relaxed pitch will be presented and discussed.

Spacer defined double patterning for (sub-)20nm half pitch single damascene structures

The spacer defined double patterning (SDDP) approach for 20nm half pitch (HP) single damascene Cu interconnect structures using immersion lithography is being reviewed. Final results on wafer will be shown, focusing on critical double patterning topics such as CD & overlay budget and line edge roughness (LER); and their impact on the electrical functioning of the back-end-of-line test structures. The feasibility of extending the SDDP technique down to 15nm HP structures is also discussed. The 30nm line/space structures patterned in resist, required as a starting point for this exercise, will be patterned using EUV lithography.

Saturation of front propagation in a reaction diffusion process describing plasma damage in porous low-k materials

We propose a three-component reaction-diffusion system yielding an asymptotic logarithmic time dependence for a moving interface. This is naturally related to a Stefan problem for which both one-sided Dirichlet-type and von Neumann-type boundary conditions are considered. We integrate the dependence of the interface motion on diffusion and reaction parameters and we observe a change from transport behavior and interface motion

Mass Metrology for controlling and understanding processes

~{t}^{1/2}

Process development using negative tone development for the dark field critical layers in a 28nm node process

to logarithmic behavior

CMOS patterning over high-aspect ratio topographies for N10/N7 using spin-on carbon hardmasks

~mathrm{ln}t

Formation of deep airgap trenches and related applications

as a function of time. We apply our theoretical findings to the propagation of carbon depletion in porous dielectrics exposed to a low temperature plasma. This diffusion saturation is reached after about one minute in typical experimental situations of plasma damage in microelectronic fabrication. We predict the general dependencies on porosity and reaction rates.

Integrated diffusion-recombination model for describing the logarithmic time dependence of plasma damage in porous low-k materials

In this paper we report on mass metrology used for the characterization of different process steps (etch, clean, cavity etch, HARP deposition and CMP) of shallow trench isolation (STI) module in conventional CMOS technology. We also report on mass metrology for the characterization of plasma doping and on HfO2 high k gate dielectric deposition process. The performance of the mass balance metrology is benchmarked against state of the art metrology, including ellipsometry and Rutherford Backscattering (RBS).

Effect of top power on a low-k film during oxygen strip in a TCP etch chamber

The demand for ever shrinking semiconductor devices is driving efforts to reduce pattern dimensions in semiconductor lithography. In this work, the aim is to find a single patterning litho solution for a 28nm technology node using 193nm immersion lithography. Target poly pitch is 110nm and metal1 pitch is 90nm. For this, we have introduced a range of different techniques to reach this goal. At this node, it becomes essential to include the layout itself into the optimization process. This leads to the introduction of restricted design rules, together with the co-optimization of source and mask (SMO) and the use of customized illumination modes (freeform illumination sources; FlexrayTM). Also, negative tone development (NTD) is employed to further extend the applicability of 193nm immersion lithography. Traditionally, the printing of contacts and trenches is done by using a dark field mask in combination with a positive tone resist and positive tone development. The use of negative tone development enables images reversal. This allows benefiting from the improved imaging performance when exposing with bright field masks. The same features can be printed in positive tone resists and with improved process latitudes. At the same time intermediate metal (IM) layers are used to connect the front-end and back-end-of-line, resulting in huge area benefits compared to layouts without these IM layers. The use of these IM layers will not happen for the 28nm node, but is intended to be introduced towards the 20nm node, and beyond. Nevertheless, the choice was made to use this architecture to obtain a first learning cycle on this approach. In this study, the use of negative tone development is explored, and its use for the various dark field critical layers in a 28nm node process is successfully demonstrated. In order to obtain sufficiently large process windows, structures are printed larger than the designed target CD. As a consequence, a shrink of the structures needs to be applied to obtain the target CD after etch. Different shrink approaches are compared. Final results on wafer are discussed, focusing on critical layers as IM1, IM2, Via0 and Metal1.