Soo-Young Oh

Interconnect scaling: signal integrity and performance in future high-speed CMOS designs

The impact of new interconnect materials and various circuit design techniques on both performance and signal integrity in future high-speed CMOS is investigated. Specifically, this work examines the use of copper, low-k dielectrics, repeaters, driver sizing and novel design techniques with respect to crosstalk and delay in the 0.25 to 0.07 /spl mu/m generations. We show crosstalk to be very important in scaled ULSI interconnects and steps such as reduced aspect ratios and asymmetric pitches should be used to ensure signal integrity.

An on-chip, interconnect capacitance characterization method with sub-femto-farad resolution

In this paper, a sensitive and simple technique for parasitic interconnect capacitance measurement with 0.01 fF sensitivity is presented. This on-chip technique is based upon an efficient test structure design. No reference capacitor is needed. Only a DC current meter is required for its measurement. We have applied this technique to extract various interconnect geometry capacitances and compared the results to those from 3D simulations.

A Novel Statistical Metrology Framework for Identifying Sources of Variation in Oxide Chemical‐Mechanical Polishing

A statistical metrology framework is used to identify systematic and random sources of interlevel dielectric thickness variation. Electrical and physical measurements, technology computer-aided design simulations, design of experiments, signal processing, and statistical analysis are integrated via statistical metrology to deconvolve interlevel dielectric thickness variation into constituent variation sources. In this way, insight into planarization variation is enabled; for a representative chemical/mechanical polishing process, we find that die-level neighborhood interactions are comparable to die level feature dependent effects, and that within each die, die level variation is greater than wafer level variation. The characterization of variation sources via statistical metrology is critical for improved process control, interconnect simulation, and robust circuit design.

Nondestructive Multilevel Interconnect Parameter Characterization For High-performance Manufacturable VLSI Technologies

One of the challenges in VLSI fabrication is to design submicron multilevel metals with high yield. This paper describes a concurrent engineering methodology that provides semiconductor engineers and VLSI circuit designers with an efficient test, modeling, and SPICE-level simulation environment. At the beginning of interconnect technology selection/evaluation, comprehensive and representative 3-D interconnect test structures are designed and fabricated for each technology option. The geometric parameters and their standard deviations are then characterized by measured data using 3-D-simulated ‘thickness vs. capacitance’ curves. A spreadsheet-based Universal Multilevel Interconnect Model Evaluator reads the characterized geometric parameters and generates maximum-, nominal-, and minimum-case parameterized interconnect SPICE subcircuits for each technology to model global and critical VLSI interconnect networks, such as clock trees, power distribution, control/data buses, and word/bit lines. In this way, new interconnect options can be evaluated using rigorous SPICE simulations.