Stephen Parke

Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI

In this paper, we propose a novel operation of a MOSFET that is suitable for ultra-low voltage (0.6 V and below) VLSI circuits. Experimental demonstration was carried out in a Silicon-On-Insulator (SOI) technology. In this device, the threshold voltage of the device is a function of its gate voltage, i.e., as the gate voltage increases the threshold voltage (V/sub t/) drops resulting in a much higher current drive than standard MOSFET for low-power supply voltages. On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low. We provide extensive experimental results and two-dimensional (2-D) device and mixed-mode simulations to analyze this device and compare its performance with a standard MOSFET. These results verify excellent inverter dc characteristics down to V/sub dd/=0.2 V, and good ring oscillator performance down to 0.3 V for Dynamic Threshold-Voltage MOSFET (DTMOS).

A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation

To extend the lower bound of power supply to ultra-low voltages (0.6 V and below), we propose a dynamic-threshold voltage MOSFET (DTMOS) built on silicon-on-insulator (SOI). The threshold voltage of DTMOS drops as the gate voltage is raised, resulting in a much higher current drive than standard MOSFET at low power supply voltages. On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low. We provide experimental results and 2-D device and mixed-mode simulations to analyze DTMOS and compare its performance with a standard MOSFET. These results verify excellent DC inverter characteristics down to V/sub dd/=0.2 V, and good ring oscillator performance down to 0.3 V for DTMOS.<<ETX>>

A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation

A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V/sub dd/. On the other hand, V/sub t/ is high at V/sub gs/=0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V/sub dd/=0.5 V.<<ETX>>

Design for suppression of gate-induced drain leakage in LDD MOSFETs using a quasi-two-dimensional analytical model

A systematic study of gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described. Design curves quantifying the GIDL dependence on gate oxide thickness, phosphorus dose, and spacer length are presented. In addition, a new, quasi-2-D analytical model is developed for the electric field in the gate-to-drain overlap region. This model successfully explains the observed GIDL dependence on the lateral doping profile of the drain. Also, a technique is proposed for extracting this lateral doping profile using the measured dependence of GIDL current on the applied substrate bias. Finally, the GIDL current is found to be much smaller in lightly doped LDD devices than in SD or fully overlapped LDD devices, due to smaller vertical and lateral electric fields. However, as the phosphorus dose approaches 10/sup 14//cm/sup 2/, the LDD and fully overlapped LDD devices exhibit similar GIDL current. >

A high-performance lateral bipolar transistor fabricated on SIMOX

Double-diffused, lateral n-p-n bipolar transistors were fabricated in a simple CMOS-like process using SIMOX silicon-on-insulator (SOI) substrates. Excellent device characteristics were achieved, with peak h/sub FE/=120, BV/sub CEO/=10 V, and peak f/sub t/=4.5 GHz. The f/sub t/ versus BV/sub CEO/ trade-off was studied as a function of n/sup -/ collector width. f/sub t/>25 GHz is predicted for this structure with an improved device layout and optimized basewidth. This process may be easily extended in order to fabricate complementary BJTs in a C-BiCMOS thin-film SOI technology.<<ETX>>

Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs (MESFETs read MOSFETs)

A hybrid mode of device operation, in which both bipolar and MOSFET currents flow simultaneously, has been experimentally investigated using quarter-micrometer-channel-length MOSFETs which were fabricated on SIMOX silicon-on-insulator substrates. This mode of device operation is achieved by connecting the gate of a non-fully-depleted SOI MOSFET to the edges of its floating body. Both the maximum G/sub m/ and current drive at 1.5* higher than the MOSFETs normal mode. Bipolar-junction-transistor (BJT)-like 60-mV/decade turn-off behavior is also achieved. This mode of operation is very promising for low-voltage, low-power, very-high-speed logic as well as for on-chip analog functions.<<ETX>>

Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance

A new recessed-channel SOI (RCSOI) technology has been developed for fabricating ultrathin SOI MOSFETs with low source/drain series resistance. Thin-film fully depleted SOI MOSFETs with channel film thickness of 72 nm have been fabricated with the RCSOI technology. The new structure demonstrated a 70% reduction in source/drain series resistance compared with conventional processes. In the deep-submicron region, more than 80% improvement in saturation drain current and transconductance over conventional devices was achieved using the RCSOI technology. The new technology would also facilitate the use of silicide for further reducing the series resistance.<<ETX>>

High-performance sub-quarter-micrometer PMOSFET's on SOI

PMOS transistors with effective channel lengths down to 0.15 mu m have been fabricated on silicon-on-insulator (SOI) films. Gate oxide thicknesses of 5.5 and 10 nm are used. These P/sup +/ gate PMOS devices exhibit excellent short-channel behavior, low-source-drain resistance, and remarkably large current drive and transconductance. for T/sub ox/=5.5 nm, saturation transconductances of 274 mS/mm at 300 K and 352 mS/mm at 80 K are achieved, which are the highest reported values for this oxide thickness. The result is attributed to low series resistance, forward-bias body effect, and the reduction of body charge effect.<<ETX>>

Study of current drive in deep sub-micrometer SOI PMOSFET'S

Sub-quarter micrometer PMOSFETs are fabricated on SOI films, exhibiting excellent short channel behavior low source-drain resistance, and remarkably large current drive and transconductance. For T/sub ox/=5.5 nm, saturation transconductances of 270 mS/mm at 300 K and 350 mS/mm at 80 K are achieved, which are the highest reported values for this oxide thickness. Direct measurements and simulation results show that the improved current drive is due to low series resistance, forward bias body effect and the reduction of body charge effect.<<ETX>>