Hassen Aziza

EEPROM Diagnosis Based on Threshold Voltage Embedded Measurement

Knowing, that the threshold voltage of the EEPROM memory cells is a key parameter to determine the overall performance of the memory, a built in structure to extract this information is a very relevant choice to fast diagnose the failure in the memory. Thus, the objective of this paper is to present a built in self-diagnosis of EEPROM memory cells, based on threshold voltage extraction. In order to extract the threshold voltage, the modified circuit and the associated test sequence are presented. Based on the threshold voltage extraction, complementary information is proposed to improve the classical memory diagnosis methodology.

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories

Emerging non-volatile memories (NVM) based on resistive switching mechanism (RS) such as STT-MRAM, OxRRAM and CBRAM etc., are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power and good endurance (e.g., > 1012) beyond mainstream NVMs, which allow them to be embedded directly with logic units for computing purpose. This integration could increase significantly the power/die area efficiency, and then overcome definitively the power/speed bottlenecks of modern VLSIs. This paper presents firstly a theoretical investigation of synchronous NV logic gates based on RS memories (RS-NVL). Special design techniques and strategies are proposed to optimize the structure according to different resistive characteristics of NVMs. To validate this study, we simulated a non-volatile full-adder (NVFA) with two types of NVMs: STT-MRAM and OxRRAM by using CMOS 40 nm design kit and compact models, which includes related physics and experimental parameters. They show interesting power, speed and area gain compared with synchronized CMOS FA while keeping good reliability.

Robust Compact Model for Bipolar Oxide-Based Resistive Switching Memories

Emerging nonvolatile memories based on resistive switching mechanisms pull intense research and development efforts from both academia and industry. Oxide-based resistive random access memories (OxRAM) gather noteworthy performances, such as fast WRITE/READ speed, low power, high endurance, and large integration density that outperform conventional flash memories. To fully explore new design concepts, such as distributed memory in logic or biomimetic architectures, robust OxRAM compact models must be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we propose a physics-based compact model used in electrical simulator for bipolar OxRAM memories. After uncovering the theoretical background and the set of relevant physical parameters, this model is confronted to experimental electrical data. The excellent agreement with these data suggests that this model can be confidently implemented into circuit simulators for design purpose.

Nonvolatile memories: Present and future challenges

Due to the rapid development of hand-held electronic devices, the need for high density, low power, high performance SoCs has pushed the well-established embedded memory technologies to their limits. To overcome the existing memory issues, emerging memory technologies are being developed and implemented. The focus is placed on non-volatile technologies, which should meet the high demands of tomorrow applications. The nonvolatile memory technologies being intensively researched today are the Flash memories and the emerging resistive and magnetic type random access memories. This paper presents an overview of device level operation of these nonvolatile memories, with special emphasis on the fabrication-and aging-induced reliability issues.

Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate

Embedded DRAM technology is undergoing a radical evolution. With size reduction, capacity shrink seems to be a complex obstacle to overcome. Alternative memory cells have been proposed to respond to this problem; capacitorless eDRAM is one of most promising solution. In this paper, after reviewing the current status on eDRAM market and recent evolution of eDRAM trends we study the feasibility of an innovative capacitorless eDRAM based on intrinsic bipolar transistor on bulk substrate.

Evaluation of OxRAM cell variability impact on memory performances through electrical simulations

An investigation in the impact of Oxide-based Resistive Memory RAM devices (OxRRAM) variability on the memory array performances is proposed. Variability in advanced IC designs has emerged as a roadblock and significant efforts of process and design engineers are required to decrease its impact. This is especially true for OxRRAM memory, combining high level of integration with exotic materials. In this study, electrical simulations, based on an OxRRAM compact model, are performed at a circuit level. Simulation results are analyzed in terms of OxRRAM cells electrical characteristic variations to evaluate the robustness of the memory array.

Bipolar OxRRAM memory array reliability evaluation based on fault injection

In this paper, a fault injection and simulation approach is used to study effects of resistive and capacitive defects on the faulty behavior of Oxide-based Resistive Memory RAM devices (OxRRAM). During the memory operations, logical and electrical characteristics of each memory cell of an elementary array are evaluated by using a bipolar OxRRAM compact model calibrated on actual devices. Simulation results are analyzed in terms of OxRRAM electrical characteristic variations to evaluate the robustness of the memory array against injected defects, inherent to the routing circuitry.

Development of a CMOS Oscillator Concept for Particle Detection and Tracking

An oscillator concept developed for particle detection and tracking is presented. The methodology used to characterize the currents generated by the particle is detailed. A Design Of Experiment (DOE) analysis is used to correlate the circuit oscillations with the current characteristics after particle detection. To validate the concept, an application example is developed to validate the detector capability to track a striking particle.

Compact modeling solutions for OxRAM memories

Emerging non-volatile memories based on resistive switching mechanisms pull intense R&D efforts from both academia and industry. Oxide-based Resistive Random Acces Memories (namely OxRAM) gather noteworthy performances, such as fast write/read speed, low power and high endurance outperforming therefore conventional Flash memories. To fully explore new design concepts such as distributed memory in logic, OxRAM compact models have to be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we present an compact models of the bipolar OxRAM memory based on physical phenomenons. This model was implemented in electrical simulators for single device up to circuit level.

Crossbar architecture based on 2R complementary resistive switching memory cell

Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012) beyond Flash memories. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure enough current for the switching operation. This paper describes a design of crossbar architecture based on 2R complementary resistive switching memory cell. This architecture allows fewer selection transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture. We performed transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 65 nm design kit and memory compact models.