Dimitri De Jonghe

Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection

The paper discusses a technique to perform efficient circuit reliability analysis of large analog and mixed-signal systems. The proposed method includes the impact of both process variations and transistor aging effects. The complexity of large systems is dealt with by partitioning the system into manageable subblocks that are modeled separately. These models are then evaluated to obtain the system specifications. However, highly expensive reliability simulations, combined with nonlinear output behavior and the high dimensionality of the problem is still a very challenging task. Therefore the use of fast function extraction symbolic regression (FFX) is proposed. This allows to capture the high-dimensional nonlinear problem with good accuracy. Also, an active learning sample selection algorithm is introduced to minimize the amount of expensive aging simulations. The algorithm trades of space exploration with function nonlinearity detection and model uncertainty reduction to select optimal model training samples. The simulation method is demonstrated on a 6 bit Flash ADC, designed in a 32nm CMOS technology. Experimental results show a speedup of 360× over existing aging simulators to evaluate 100 Monte-Carlo samples with good accuracy.

Stochastic Macromodeling of Nonlinear Systems Via Polynomial Chaos Expansion and Transfer Function Trajectories

A novel approach is presented to perform stochastic variability analysis of nonlinear systems. The versatility of the method makes it suitable for the analysis of complex nonlinear electronic systems. The proposed technique is a variation-aware extension of the Transfer Function Trajectory method by means of the Polynomial Chaos expansion. The accuracy with respect to the classical Monte Carlo analysis is verified by means of a relevant numerical example showing a simulation speedup of 1777×.

Characterization of Analog Circuits Using Transfer Function Trajectories

A methodology is presented to characterize and model strongly nonlinear behavior of analog circuits with a compact set of nonlinear differential equations. While simulating a circuit in the time domain, the nodal matrix is extracted at each time step, similar to trajectory piecewise sampling (TPW). The circuit snapshots projected on a frequency-state space domain to facilitate the regression problem, based upon the vector fitting algorithm. Strongly nonlinear function approximation of the pole-residue trajectories render analytical models with very high accuracy, even with a limited training sequence. The proposed method proves to scale very well for large circuits with speedups that exceed the TPW implementation. The method is compatible with SPICE3f5 netlisting and commercial CMOS technologies and the models are easily exported as a state space description to behavioral languages such as VHDL-AMS or Verilog-AMS. The method is validated for analog circuits of medium and large size.

Efficient analytical macromodeling of large analog circuits by transfer function trajectories

Automated abstraction of large analog circuits greatly improves simulation time in custom analog design flows. Due to the high degree of variety of circuits this task is mainly a manual ad-hoc approach. This paper proposes an automated modeling approach for large scale analog circuits that produces compact expressions from a SPICE netlist. The presented method builds upon the state-of-the-art Trajectory PieceWise (TPW) approach. Because of their data-driven nature, TPW implementations generate models that require on-the-fly database interpolation during simulation, which is not embedded in a standard commercial design flow. Our approach solves this by recombining TPW samples as a surface in a mixed state space-frequency domain, revealing information about the circuits nonlinear behavior. The resulting data, termed Transfer Function Trajectories (TFT), is fitted with a parametric vector fitting algorithm and further translated to system blocks. These are compatible with VHDL-AMS/Verilog-AMS, Matlab/Simulink or hand calculations at all design stages. The models show high accuracy and a speedup of 10×–40× against the ELDO simulator for large circuits up to 150 nodes.

Extracting analytical nonlinear models from analog circuits by recursive vector fitting of transfer function trajectories

This paper presents a technique for automatically extracting analytical behavioral models from the netlist of a nonlinear analog circuit. Subsequent snapshots of the internal circuit Jacobian are sampled during time-domain analysis and are then processed into Transfer Function Trajectories (TFT). The TFT data project the nonlinear dynamics of the system onto a hyperplane in the mixed state-space/frequency domain. Next Recursive Vector Fitting (RVF) algorithm is used to extract an analytical Hammerstein model out of the TFT data in an automated fashion. The resulting RVF model equations are implemented as an accurate nonlinear behavioral model in the time domain. The model is guaranteed stable by construction and can trade off complexity for accuracy. The technique is validated on a high-speed analog buffer circuit containing 70 linear and nonlinear components, showing a 7X speedup.

Advances in variation-aware modeling, verification, and testing of analog ICs

This tutorial paper describes novel scalable, nonlinear/generic, and industrially-oriented approaches to perform variation-aware modeling, verification, fault simulation, and testing of analog/custom ICs. In the first section, Dimitri De Jonghe, Elie Maricau, and Georges Gielen present a new advance in extracting highly nonlinear, variation-aware behavioral models, through the use of data mining and a re-framing of the model-order reduction problem. In the next section, Trent McConaghy describes new statistical machine learning techniques that enable new classes of industrial EDA tools, which in turn are enabling designers to perform fast and accurate PVT / statistical / high-sigma design and verification. In the third section, Bratislav Tasić presents a novel industrially-oriented approach to analog fault simulation that also has applicability to variation-aware design. In the final section, Haralampos Stratigopoulos describes describes state-of-the-art analog testing approaches that address process variability.

Optimization of fully-integrated power converter circuits comprising tapered inductor layout and temperature effects

A technique for the optimization of fully-integrated inductive DC-DC converters is presented. An optimization framework is used to acquire an optimal converter, focusing on the on-chip inductor as well as on the accurate layout-based modeling of temperature effects. For the inductor in inductive DC-DC converters, a tapered topology is introduced. A fully-integrated DC-DC boost converter is designed and optimized in a 0.13 μm CMOS technology. The power loss in the circuit is reduced with 27 % resulting in a 7 % efficiency improvement, compared to a fully-integrated DC-DC boost converter with a regular inductor topology.

Less expensive and high quality stopping criteria for MC-based analog IC yield optimization

This paper investigates the stopping criteria for Monte-Carlo (MC)-based yield optimization of analog integrated circuits. Available stopping criteria are briefly reviewed and a new adaptive criterion, called combined global and local improvement (ComImp) is presented. Experimental results show that the proposed stopping criterion has the following two advantages: (1) low risk of early termination before the optimum has been reached with the desired accuracy; (2) less additional function evaluations after the convergence has already been reached.

Towards automated extraction of EMC-aware trajectory-based macromodels for analog circuits

In this paper a new methodology is proposed for automated generation of EMC-aware behavioral models. Tightening EMC regulations require elaborate testing and simulation of EMC susceptibility of analog circuits during the design stage. A classification strategy detects EMC-sensitive devices which allows us to incorporate a more elaborate device model when accuracy is needed due to rectification effects. In addition, trajectory-based models are used for efficient modeling of nonlinear dynamical systems. Trajectory methods sample the state space trajectory of a circuit while exciting the circuit with a representative training input. The macromodel is generated by reduction and interpolation of linearizations among the sampled trajectory points, in which the validity of the model is defined. Without relevant loss of accuracy, the simulation time of larger systems for EMC can be reduced with an order of magnitude. The method is verified on a single-stage opamp with rectifying bias current mirror, a circuit exhibiting EMC distortion.

Automatic generation of electro-thermal models with TRAPPIST

It has been shown that the transfer function trajectories (TFT) approach allows the automated extraction of compact behavioral models for analog and mixed-signal circuit blocks. The models consist in the concatenation of a multiple-input-multiple-output (MIMO) linear filtering stage and a nonlinear scheduling stage, ensuring a very broad coverage for the method. Models that are generated with the TRAPPIST method (TRajectory Approximation by the Identification of State-dependent Transfer functions) were shown capable of achieving adjustable error versus complexity trade-offs to reproduce the response of any arbitrary realization and to account for voltage variations and stochastical design parameters. In this paper, the TRAPPIST method is used to create an electro-thermal behavioral model of the circuit, by merging data from a (pure) thermal simulator and from standard iso-thermal circuit simulations. The resulting TFT model has an error below 2% and allows to alter the temperature dynamically during time-domain simulations.