Elie Maricau

Emerging yield and reliability challenges in nanometer CMOS technologies

With further scaling of nanometer CMOS technologies, yield and reliability become an increasing challenge. This paper reviews the most important phenomena affecting yield and reliability. For each effect, the basic physical mechanisms causing the effect and its impact on transistor parameters are described. Possible solutions to cope/handle with these effects on the design level are discussed as well.

Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS

Integrated analog circuit design in nanometer CMOS technologies brings forth new and significant reliability challenges. Ever-increasing process variability effects and transistor wear-out phenomena such as BTI, hot carrier degradation and dielectric breakdown force designers to use large design margins and to increase the uncertainty on the circuit lifetime. To help designers to tackle these problems at design time (i.e., Design For Reliability, or DFR), accurate transistor aging models, efficient circuit reliability analysis methods and novel design techniques are needed. The paper overviews the current state of the art in DFR for analog circuits. The most important unreliability effects in nanometer CMOS technologies are reviewed and transistor aging models, intended for accurate circuit simulation, are described. Also, efficient methods for circuit reliability simulation and analysis are discussed. These methods can help designers to analyze their circuits and to identify weak spots. Finally, cost-effective design techniques for more resilient and self-healing analog circuits are studied.

Analog IC reliability in nanometer CMOS

Today, micro-electronic circuits are undeniably and ubiquitously present in our society. Transportation vehicles such as cars, trains, buses, and airplanes make abundant use of electronic circuits to reduce energy consumption and emission of greenhouse gases and to increase passenger safety and travel comfort. Other products using electronic circuits are smartphones, tablet PCs, game consoles, household appliances, satellites, base stations, servers, etc. Each of these applications is becoming increasingly more complex to build. At the same time, the quality and reliability requirements for electronic circuits are more demanding than ever. To guarantee a high production yield and a sufficient circuit lifetime, possible hazards and failure effects have to be considered throughout the entire design flow. Such a flow includes the initial concept, the design itself, the testing of the prototype circuit, and finally the production process. The majority of integrated circuits manufactured today is processed in a complementary metal-oxide semiconductor (CMOS) technology. To reduce cost and to increase performance, the dimensions of all circuit components are shrinked with each new technology node. Associated with this technology scaling are the atomistic size of modern transistors, an increase of the gate-oxide electric field, and the introduction of new gate and channel materials. The combination of these elements results in an emerging reliability problem for advanced nanometer CMOS technologies. Transistor wearout manifests itself as a gradual and time-dependent shift of circuit characteristics which can result in circuit failure. Especially analog circuits, which are typically used as an interface between the real world and a digital backend, can be very sensitive to such small circuit parameter variations. This work focuses on the simulation and analysis of analog circuit reliability. The models and simulation techniques proposed in this dissertation are aimed to serve as an aid for circuit designers to better understand the impact of aging effects on their circuits and to enable the development of failure-resilient design solutions. In a first part of the work, an overview of all relevant nanometer CMOS unreliability effects is given and transistor compact models for the most important

Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis

This paper discusses an efficient method to analyze the spatial and temporal reliability of analog and digital circuits. First, a SPICE-based reliability simulator with automatic step-size control is proposed. Both hot carrier degradation and negative bias temperature instability are included in the simulator. Next, a method to analyze the interaction between process variability effects and circuit aging is introduced. This method is based on a screening experimental design (DoE) succeeded by a set of regression DoEs, resulting in a good speed-accuracy tradeoff with a nearly linear complexity for all circuits under test. Finally, based on the DoE analysis, a circuit response surface model (RSM) is derived. The RSM is used for further circuit reliability analysis such as circuit weak spot detection and yield calculation as a function of circuit lifetime. The proposed method is validated over a broad range of both analog and digital circuits. Yield simulation time is reduced with up to three orders of magnitude, when compared to standard Monte Carlo-based techniques and while still maintaining simulation accuracy.

An analytical model for hot carrier degradation in nanoscale CMOS suitable for the simulation of degradation in analog IC applications

Channel hot carrier (CHC) degradation is one of the major reliability concerns for nanoscale transistors. To simulate the impact of CHC on analog circuits, a unified analytical model able to cope with various design and process parameters is proposed. In addition, our model can handle initial degradation and varying stress conditions, allowing the designer to estimate the impact of CHC on transistor performance for arbitrary stressing patterns. The model is experimentally verified in a 65 nm CMOS technology. Expressions to simulate the impact of transistor degradation on relevant transistor parameters like output conductance and threshold voltage degradation are presented and verified.

Analog circuit reliability in sub-32 nanometer CMOS: Analysis and mitigation

The paper discusses reliability threats and opportunities for analog circuit design in high-k sub-32 nanometer technologies. Compared to older SiO2 or SiON based technologies, transistor reliability is found to be worse in high-k nodes due to larger oxide electric fields, the severely aggravated PBTI effect and increased time-dependent variability. Conventional reliability margins, based on accelerated stress measurements on individual transistors, are no longer sufficient nor adequate for analog circuit design. As a means to find more accurate, circuit-dependent reliability margins, advanced degradation effect models are reviewed and an efficient method for stochastic circuit reliability simulation is discussed. Also, an example 6-bit 32nm current-steering digital-to-analog converter is studied. Experiments demonstrate how the proposed simulation tool, combined with novel design techniques, can provide an up to 89% better area-power product of the analog part of the circuit under study, while still guaranteeing a 99.7% yield over a lifetime of 5 years.

Transistor aging-induced degradation of analog circuits: Impact analysis and design guidelines

Transistor aging effects are more and more a major concern for device scientists, trying to integrate reliable circuits in unreliable ultra-scaled CMOS processes. Circuit design margins, to guarantee reliable analog circuit operation, are no longer sufficient and result in huge circuit overdesign. This paper discusses i) the most important transistor aging effects, ii) how designers can evaluate their impact on circuits and iii) design guidelines on which circuits are sensitive to transistor aging. Circuit parameters such as amplifier gain, bandwidth and slewrate are shown to be immune to transistor aging, while variation-sensitive parameters such as offset, the output current of a current mirror and the on-resistance of a MOS-resistor are very prone to transistor aging. Furthermore, to help a designer estimate the impact of aging on his/her circuit and to find a good reliability-performance tradeoff, a first-order transistor aging model is provided.

Efficient reliability simulation of analog ICs including variability and time-varying stress

Aggressive scaling to nanometer CMOS technologies causes both analog and digital circuit parameters to degrade over time due to die-level stress effects (i.e. NBTI, HCI, TDDB, etc). In addition, failure-time dispersion increases due to increasing process variability. In this paper an innovative methodology to simulate analog circuit reliability is presented. Advantages over current state of the art reliability simulators include, among others, the possibility to estimate the impact of variability and the ability to account for the effects of complex time-varying stress signals. Results show that taking time-varying stress signals into account provides circuit reliability information not visible with classic DC-only reliability simulators. Also, variability-aware reliability simulation results indicate a significant percentage of early circuit failures compared to failure-time results based on nominal design only.

Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection

The paper discusses a technique to perform efficient circuit reliability analysis of large analog and mixed-signal systems. The proposed method includes the impact of both process variations and transistor aging effects. The complexity of large systems is dealt with by partitioning the system into manageable subblocks that are modeled separately. These models are then evaluated to obtain the system specifications. However, highly expensive reliability simulations, combined with nonlinear output behavior and the high dimensionality of the problem is still a very challenging task. Therefore the use of fast function extraction symbolic regression (FFX) is proposed. This allows to capture the high-dimensional nonlinear problem with good accuracy. Also, an active learning sample selection algorithm is introduced to minimize the amount of expensive aging simulations. The algorithm trades of space exploration with function nonlinearity detection and model uncertainty reduction to select optimal model training samples. The simulation method is demonstrated on a 6 bit Flash ADC, designed in a 32nm CMOS technology. Experimental results show a speedup of 360× over existing aging simulators to evaluate 100 Monte-Carlo samples with good accuracy.

Stochastic circuit reliability analysis

Stochastic circuit reliability analysis, as decribed in this work, matches the statistical attributes of underlying device fabrics and transistor aging to the spatial and temporal reliability of an entire circuit. For the first time, spatial and temporal stochastic and deterministic reliability effects are handled toghether in an efficient framework. The paper first introduces an equivalent transistor SPICE model, comprising the currently most important aging effects (i.e NBTI, hot carriers and soft breakdown). A simulation framework then uses this SPICE model to minimize the number of circuit factors and to build a circuit model. The latter allows for example very fast circuit yield analysis. Using experimental design techniques the proposed method is very efficient and also proves to be very flexible. The simulation technique is demonstrated on an example 6-bit current-steering DAC, where the creation of soft breakdown spots can result in circuit failure due to increasing time-dependent transistor mismatch.