Piet Callemeyn

DC-DC converters: From discrete towards fully integrated CMOS

Monolithic integration of electronic systems is one of the major techniques to reduce cost, size and power consumption in state-of-the-art consumer applications. Integration of transceivers and other mixed-signal building blocks has proven to be a very successful approach to build low cost, compact and portable systems [1]. Remarkably a certain building block remains discrete in commercial applications: the switched-power supply. This paper will demonstrate how recent research efforts cleared the path to develop fully integrated DC-DC converters in standard CMOS.

Optimization of fully-integrated power converter circuits comprising tapered inductor layout and temperature effects

A technique for the optimization of fully-integrated inductive DC-DC converters is presented. An optimization framework is used to acquire an optimal converter, focusing on the on-chip inductor as well as on the accurate layout-based modeling of temperature effects. For the inductor in inductive DC-DC converters, a tapered topology is introduced. A fully-integrated DC-DC boost converter is designed and optimized in a 0.13 μm CMOS technology. The power loss in the circuit is reduced with 27 % resulting in a 7 % efficiency improvement, compared to a fully-integrated DC-DC boost converter with a regular inductor topology.

From AC to DC and reverse, the next fully integrated power management challenge

This chapter discusses the advances of the next leap in integrated power management beyond the scope of today’s DC-DC converters: the interaction with AC. Both AC to DC and DC to AC conversion with the intention of eventually interfacing mains voltages are investigated and reported on. The AC-DC conversion research aims to interface the mains voltage while achieving a high level of integration and compatibility to low voltage CMOS circuits, enabling power supply straight from the wall socket. Alternatively the reverse interaction from DC to AC is investigated similarly and targets inversion of low voltage DC values to higher AC values for driving purposes. Because of the integrated approach, the bill of materials is drastically reduced.

A stacked full-bridge topology for high voltage DC-AC conversion in standard CMOS technology

A monolithic DC-AC converter is realized in a 130 nm 1.2V CMOS technology using a Class-D half-bridge topology. Several dies are combined to achieve a full-bridge topology, realizing a bipolar output voltage. Using a stacking technique, this output voltage can be increased. This yields AC output voltages up to 4V, which is more than three times the nominal 1.2V supply voltage of the technology. The passives are integrated on-chip. Consequently, the bill of materials (BOM) is heavily reduced. In a standard half-bridge topology, bulky external capacitors are needed to filter out the DC offset. This main obstacle of an off-chip capacitor is alleviated in the full-bridge topology, reducing the BOM even more. An output peak-to-peak voltage of 3.8V is achieved at a maximal efficiency of 58.3%. A total output power of 56mW is obtained.

Monolithic integration of a class DE inverter for on-chip resonant DC-DC converters

A fully-integrated series resonant class DE inverter is realized in a 130 nm 1.2 V CMOS technology with an on-chip spiral inductor and an integrated MIMcap. It is used as the first stage in fully-integrated class DE DC-DC resonant converters. The inherent soft switching yields high conversion efficiency at high switching frequencies. Low switching peak-voltages are present in the circuit, alleviating the need for on-chip high-voltage techniques. The use of on-chip passives reduces the bill of materials (BOM) considerably. The maximum output power of the series resonant class DE inverter is 11.6 mW. The maximum power efficiency is 65.2 %. The measurement results confirm and improve previous simulations.

A monolithic stacked Class-D approach for high voltage DC-AC conversion in standard CMOS

A fully-integrated Class-D DC-AC converter is realized in a 130 nm 1.2V CMOS technology with an on-chip inductor and capacitor. Several dies are combined to achieve higher output power. A multilevel topology allows the combined Class-D DC-AC system to achieve higher output voltages at a multiple of the nominal supply voltage of 1.2V. Problems such as hot carrier degradation and oxide breakdown are absent, since each subblock operates within the standard voltage limits. An off-chip low frequency signal can be used as a reference clock for the Class-D DC-AC converter using an on-chip PWM generation circuit. For this monolithic multilevel system, no discrete components are needed anymore, reducing the bill of materials. A maximum efficiency of 66.5% for a stand-alone die is reached. An output peak voltage of 2.4V peak-to-peak is achieved at an efficiency of 33% by using a combination of several dies. A total output power of 95mW is obtained.